This patch introduces new library callback (ArmadaSoCPcieGet ()),
which dynamically allocates and fills array with all available PCIE
controllers' base addresses. It is needed for the configuration of PCIE,
whose support will be added in the upcoming patches.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 6 +++
Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 20 +++++++++
Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 44 ++++++++++++++++++++
3 files changed, 70 insertions(+)
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
index 8bbc5b0..e904222 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
@@ -82,6 +82,12 @@
#define MV_SOC_MDIO_ID(Cp) (Cp)
//
+// Platform description of PCIE
+//
+#define MV_SOC_PCIE_PER_CP_COUNT 3
+#define MV_SOC_PCIE_BASE(Index) (0x600000 + ((Index) * 0x20000))
+
+//
// Platform description of PP2 NIC
//
#define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE (Cp)
diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
index fc17c3a..ff617e6 100644
--- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
+++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
@@ -191,6 +191,26 @@ ArmadaSoCDescXhciGet (
IN OUT UINTN *DescCount
);
+/**
+ This function returns the total number of PCIE controllers and an array
+ with their base addresses.
+
+ @param[in out] **PcieBaseAddresses Array containing PCIE controllers' base
+ adresses.
+ @param[in out] *Count Total amount of available PCIE controllers.
+
+ @retval EFI_SUCCESS The data were obtained successfully.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
+ lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+ArmadaSoCPcieGet (
+ IN OUT EFI_PHYSICAL_ADDRESS **PcieBaseAddresses,
+ IN OUT UINTN *Count
+ );
+
//
// PP2 NIC devices SoC description
//
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
index 355be64..4f8a59a 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
@@ -278,6 +278,50 @@ ArmadaSoCDescAhciGet (
return EFI_SUCCESS;
}
+/**
+ This function returns the total number of PCIE controllers and an array
+ with their base addresses.
+
+ @param[in out] **PcieBaseAddresses Array containing PCIE controllers' base
+ adresses.
+ @param[in out] *Count Total amount of available PCIE controllers.
+
+ @retval EFI_SUCCESS The data were obtained successfully.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
+ lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+ArmadaSoCPcieGet (
+ IN OUT EFI_PHYSICAL_ADDRESS **PcieBaseAddresses,
+ IN OUT UINTN *Count
+ )
+{
+ UINTN CpCount, CpIndex, Index;
+ EFI_PHYSICAL_ADDRESS *BaseAddress;
+
+ CpCount = FixedPcdGet8 (PcdMaxCpCount);
+
+ *Count = CpCount * MV_SOC_PCIE_PER_CP_COUNT;
+ BaseAddress = AllocateZeroPool (*Count * sizeof (EFI_PHYSICAL_ADDRESS));
+ if (BaseAddress == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__));
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ *PcieBaseAddresses = BaseAddress;
+
+ for (CpIndex = 0; CpIndex < CpCount; CpIndex++) {
+ for (Index = 0; Index < MV_SOC_PCIE_PER_CP_COUNT; Index++) {
+ *BaseAddress = MV_SOC_CP_BASE (CpIndex) + MV_SOC_PCIE_BASE (Index);
+ BaseAddress++;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
EFI_STATUS
EFIAPI
ArmadaSoCDescPp2Get (
--
2.7.4
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On Thu, May 09, 2019 at 11:53:30AM +0200, Marcin Wojtas wrote:
> This patch introduces new library callback (ArmadaSoCPcieGet ()),
> which dynamically allocates and fills array with all available PCIE
> controllers' base addresses. It is needed for the configuration of PCIE,
> whose support will be added in the upcoming patches.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 6 +++
> Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 20 +++++++++
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 44 ++++++++++++++++++++
> 3 files changed, 70 insertions(+)
>
> diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
> index 8bbc5b0..e904222 100644
> --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
> +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
> @@ -82,6 +82,12 @@
> #define MV_SOC_MDIO_ID(Cp) (Cp)
>
> //
> +// Platform description of PCIE
> +//
> +#define MV_SOC_PCIE_PER_CP_COUNT 3
> +#define MV_SOC_PCIE_BASE(Index) (0x600000 + ((Index) * 0x20000))
> +
> +//
> // Platform description of PP2 NIC
> //
> #define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE (Cp)
> diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
> index fc17c3a..ff617e6 100644
> --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
> +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
> @@ -191,6 +191,26 @@ ArmadaSoCDescXhciGet (
> IN OUT UINTN *DescCount
> );
>
> +/**
> + This function returns the total number of PCIE controllers and an array
> + with their base addresses.
> +
> + @param[in out] **PcieBaseAddresses Array containing PCIE controllers' base
Extra space before "Array" messes up alignment.
Either drop that or add one to the lines below.
/
Leif
> + adresses.
> + @param[in out] *Count Total amount of available PCIE controllers.
> +
> + @retval EFI_SUCCESS The data were obtained successfully.
> + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
> + lack of resources.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +ArmadaSoCPcieGet (
> + IN OUT EFI_PHYSICAL_ADDRESS **PcieBaseAddresses,
> + IN OUT UINTN *Count
> + );
> +
> //
> // PP2 NIC devices SoC description
> //
> diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
> index 355be64..4f8a59a 100644
> --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
> +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
> @@ -278,6 +278,50 @@ ArmadaSoCDescAhciGet (
> return EFI_SUCCESS;
> }
>
> +/**
> + This function returns the total number of PCIE controllers and an array
> + with their base addresses.
> +
> + @param[in out] **PcieBaseAddresses Array containing PCIE controllers' base
> + adresses.
> + @param[in out] *Count Total amount of available PCIE controllers.
> +
> + @retval EFI_SUCCESS The data were obtained successfully.
> + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
> + lack of resources.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +ArmadaSoCPcieGet (
> + IN OUT EFI_PHYSICAL_ADDRESS **PcieBaseAddresses,
> + IN OUT UINTN *Count
> + )
> +{
> + UINTN CpCount, CpIndex, Index;
> + EFI_PHYSICAL_ADDRESS *BaseAddress;
> +
> + CpCount = FixedPcdGet8 (PcdMaxCpCount);
> +
> + *Count = CpCount * MV_SOC_PCIE_PER_CP_COUNT;
> + BaseAddress = AllocateZeroPool (*Count * sizeof (EFI_PHYSICAL_ADDRESS));
> + if (BaseAddress == NULL) {
> + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__));
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + *PcieBaseAddresses = BaseAddress;
> +
> + for (CpIndex = 0; CpIndex < CpCount; CpIndex++) {
> + for (Index = 0; Index < MV_SOC_PCIE_PER_CP_COUNT; Index++) {
> + *BaseAddress = MV_SOC_CP_BASE (CpIndex) + MV_SOC_PCIE_BASE (Index);
> + BaseAddress++;
> + }
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> EFI_STATUS
> EFIAPI
> ArmadaSoCDescPp2Get (
> --
> 2.7.4
>
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pt., 10 maj 2019 o 16:59 Leif Lindholm <leif.lindholm@linaro.org> napisał(a):
>
> On Thu, May 09, 2019 at 11:53:30AM +0200, Marcin Wojtas wrote:
> > This patch introduces new library callback (ArmadaSoCPcieGet ()),
> > which dynamically allocates and fills array with all available PCIE
> > controllers' base addresses. It is needed for the configuration of PCIE,
> > whose support will be added in the upcoming patches.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> > ---
> > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 6 +++
> > Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 20 +++++++++
> > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 44 ++++++++++++++++++++
> > 3 files changed, 70 insertions(+)
> >
> > diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
> > index 8bbc5b0..e904222 100644
> > --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
> > +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
> > @@ -82,6 +82,12 @@
> > #define MV_SOC_MDIO_ID(Cp) (Cp)
> >
> > //
> > +// Platform description of PCIE
> > +//
> > +#define MV_SOC_PCIE_PER_CP_COUNT 3
> > +#define MV_SOC_PCIE_BASE(Index) (0x600000 + ((Index) * 0x20000))
> > +
> > +//
> > // Platform description of PP2 NIC
> > //
> > #define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE (Cp)
> > diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
> > index fc17c3a..ff617e6 100644
> > --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
> > +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
> > @@ -191,6 +191,26 @@ ArmadaSoCDescXhciGet (
> > IN OUT UINTN *DescCount
> > );
> >
> > +/**
> > + This function returns the total number of PCIE controllers and an array
> > + with their base addresses.
> > +
> > + @param[in out] **PcieBaseAddresses Array containing PCIE controllers' base
>
> Extra space before "Array" messes up alignment.
> Either drop that or add one to the lines below.
>
That's an effect of :%s typo fixing... Will correct in v2.
Thanks,
Marcin
>
> > + adresses.
> > + @param[in out] *Count Total amount of available PCIE controllers.
> > +
> > + @retval EFI_SUCCESS The data were obtained successfully.
> > + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
> > + lack of resources.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +ArmadaSoCPcieGet (
> > + IN OUT EFI_PHYSICAL_ADDRESS **PcieBaseAddresses,
> > + IN OUT UINTN *Count
> > + );
> > +
> > //
> > // PP2 NIC devices SoC description
> > //
> > diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
> > index 355be64..4f8a59a 100644
> > --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
> > +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
> > @@ -278,6 +278,50 @@ ArmadaSoCDescAhciGet (
> > return EFI_SUCCESS;
> > }
> >
> > +/**
> > + This function returns the total number of PCIE controllers and an array
> > + with their base addresses.
> > +
> > + @param[in out] **PcieBaseAddresses Array containing PCIE controllers' base
> > + adresses.
> > + @param[in out] *Count Total amount of available PCIE controllers.
> > +
> > + @retval EFI_SUCCESS The data were obtained successfully.
> > + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
> > + lack of resources.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +ArmadaSoCPcieGet (
> > + IN OUT EFI_PHYSICAL_ADDRESS **PcieBaseAddresses,
> > + IN OUT UINTN *Count
> > + )
> > +{
> > + UINTN CpCount, CpIndex, Index;
> > + EFI_PHYSICAL_ADDRESS *BaseAddress;
> > +
> > + CpCount = FixedPcdGet8 (PcdMaxCpCount);
> > +
> > + *Count = CpCount * MV_SOC_PCIE_PER_CP_COUNT;
> > + BaseAddress = AllocateZeroPool (*Count * sizeof (EFI_PHYSICAL_ADDRESS));
> > + if (BaseAddress == NULL) {
> > + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__));
> > + return EFI_OUT_OF_RESOURCES;
> > + }
> > +
> > + *PcieBaseAddresses = BaseAddress;
> > +
> > + for (CpIndex = 0; CpIndex < CpCount; CpIndex++) {
> > + for (Index = 0; Index < MV_SOC_PCIE_PER_CP_COUNT; Index++) {
> > + *BaseAddress = MV_SOC_CP_BASE (CpIndex) + MV_SOC_PCIE_BASE (Index);
> > + BaseAddress++;
> > + }
> > + }
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > EFI_STATUS
> > EFIAPI
> > ArmadaSoCDescPp2Get (
> > --
> > 2.7.4
> >
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