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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id l25sm276668lfk.57.2019.05.09.02.53.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 May 2019 02:53:57 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-devel] [edk2-platforms: PATCH 02/14] Marvell/Library: ArmadaSoCDescLib: Add PCIE information Date: Thu, 9 May 2019 11:53:30 +0200 Message-Id: <1557395622-32425-3-git-send-email-mw@semihalf.com> In-Reply-To: <1557395622-32425-1-git-send-email-mw@semihalf.com> References: <1557395622-32425-1-git-send-email-mw@semihalf.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1557395641; bh=oMV9kcTIOXIVqSvjtc2e3TetRHiZIRdTekBDqbk6WDA=; h=Cc:Date:From:Reply-To:Subject:To; b=QqkJgh1RFL+QrGt+yx+bttEM5ksxSdcdQOs5xz3t4ROmlPVNAJG1QacQ7z8x2Rt9xgD gzLqw9mo43EqSWxa5UaamrzUA4wYCtYEX1TcTPS5JZeKghoCXw+QjLTY8n0YP6cjvgCi3 HJFuF1sGtd/kWruhq8Gc+JnA/vPXLLhlmis= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callback (ArmadaSoCPcieGet ()), which dynamically allocates and fills array with all available PCIE controllers' base addresses. It is needed for the configuration of PCIE, whose support will be added in the upcoming patches. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 6 +++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 20 +++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 44 ++++++++++++++++++++ 3 files changed, 70 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h index 8bbc5b0..e904222 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -82,6 +82,12 @@ #define MV_SOC_MDIO_ID(Cp) (Cp) =20 // +// Platform description of PCIE +// +#define MV_SOC_PCIE_PER_CP_COUNT 3 +#define MV_SOC_PCIE_BASE(Index) (0x600000 + ((Index) * 0x20000)) + +// // Platform description of PP2 NIC // #define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE (Cp) diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index fc17c3a..ff617e6 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -191,6 +191,26 @@ ArmadaSoCDescXhciGet ( IN OUT UINTN *DescCount ); =20 +/** + This function returns the total number of PCIE controllers and an array + with their base addresses. + + @param[in out] **PcieBaseAddresses Array containing PCIE controllers' b= ase + adresses. + @param[in out] *Count Total amount of available PCIE contro= llers. + + @retval EFI_SUCCESS The data were obtained successfully. + @retval EFI_OUT_OF_RESOURCES The request could not be completed du= e to a + lack of resources. + +**/ +EFI_STATUS +EFIAPI +ArmadaSoCPcieGet ( + IN OUT EFI_PHYSICAL_ADDRESS **PcieBaseAddresses, + IN OUT UINTN *Count + ); + // // PP2 NIC devices SoC description // diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 355be64..4f8a59a 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -278,6 +278,50 @@ ArmadaSoCDescAhciGet ( return EFI_SUCCESS; } =20 +/** + This function returns the total number of PCIE controllers and an array + with their base addresses. + + @param[in out] **PcieBaseAddresses Array containing PCIE controllers' ba= se + adresses. + @param[in out] *Count Total amount of available PCIE contro= llers. + + @retval EFI_SUCCESS The data were obtained successfully. + @retval EFI_OUT_OF_RESOURCES The request could not be completed du= e to a + lack of resources. + +**/ +EFI_STATUS +EFIAPI +ArmadaSoCPcieGet ( + IN OUT EFI_PHYSICAL_ADDRESS **PcieBaseAddresses, + IN OUT UINTN *Count + ) +{ + UINTN CpCount, CpIndex, Index; + EFI_PHYSICAL_ADDRESS *BaseAddress; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + *Count =3D CpCount * MV_SOC_PCIE_PER_CP_COUNT; + BaseAddress =3D AllocateZeroPool (*Count * sizeof (EFI_PHYSICAL_ADDRESS)= ); + if (BaseAddress =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + *PcieBaseAddresses =3D BaseAddress; + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + for (Index =3D 0; Index < MV_SOC_PCIE_PER_CP_COUNT; Index++) { + *BaseAddress =3D MV_SOC_CP_BASE (CpIndex) + MV_SOC_PCIE_BASE (Index); + BaseAddress++; + } + } + + return EFI_SUCCESS; +} + EFI_STATUS EFIAPI ArmadaSoCDescPp2Get ( --=20 2.7.4 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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