From: Hanna Hawa <hannah@marvell.com>

Update PCD paramters to be 64 bit, so that to add more flexibility
for the platforms in terms of configuring memory-mapped SPI access.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 Silicon/Marvell/Marvell.dec                       |  2 +-
 Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc     |  6 +++---
 Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf |  6 +++---
 Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.c   | 18 +++++++++---------
 4 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec
index c927078..7210ba2 100644
--- a/Silicon/Marvell/Marvell.dec
+++ b/Silicon/Marvell/Marvell.dec
@@ -139,7 +139,7 @@
 
 #SPI
   gMarvellTokenSpaceGuid.PcdSpiRegBase|0|UINT32|0x3000051
-  gMarvellTokenSpaceGuid.PcdSpiMemoryBase|0|UINT32|0x3000059
+  gMarvellTokenSpaceGuid.PcdSpiMemoryBase|0|UINT64|0x3000059
   gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|0|UINT32|0x30000052
   gMarvellTokenSpaceGuid.PcdSpiClockFrequency|0|UINT32|0x30000053
 
diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
index 0ced400..a1ebb81 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
@@ -396,11 +396,11 @@
   # Variable store - default values
   #
   gMarvellTokenSpaceGuid.PcdSpiMemoryBase|0xF9000000
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0xF93C0000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0xF93C0000
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0xF93D0000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0xF93D0000
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0xF93E0000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0xF93E0000
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
 
 !if $(CAPSULE_ENABLE)
diff --git a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf b/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf
index fd3f2f7..ef10bfd 100644
--- a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf
+++ b/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf
@@ -76,11 +76,11 @@
   gMarvellSpiMasterProtocolGuid
 
 [FixedPcd]
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
   gMarvellTokenSpaceGuid.PcdSpiMemoryBase
 
diff --git a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.c b/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.c
index 1a41a4f..cb006cd 100644
--- a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.c
+++ b/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.c
@@ -145,12 +145,12 @@ MvFvbInitFvAndVariableStoreHeaders (
   // FirmwareVolumeHeader->FvLength is declared to have the Variable area
   // AND the FTW working area AND the FTW Spare contiguous.
   //
-  ASSERT (PcdGet32 (PcdFlashNvStorageVariableBase) +
+  ASSERT (PcdGet64 (PcdFlashNvStorageVariableBase64) +
     PcdGet32 (PcdFlashNvStorageVariableSize) ==
-    PcdGet32 (PcdFlashNvStorageFtwWorkingBase));
-  ASSERT (PcdGet32 (PcdFlashNvStorageFtwWorkingBase) +
+    PcdGet64 (PcdFlashNvStorageFtwWorkingBase64));
+  ASSERT (PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) +
     PcdGet32 (PcdFlashNvStorageFtwWorkingSize) ==
-    PcdGet32 (PcdFlashNvStorageFtwSpareBase));
+    PcdGet64 (PcdFlashNvStorageFtwSpareBase64));
 
   // Check if the size of the area is at least one block size
   ASSERT ((PcdGet32 (PcdFlashNvStorageVariableSize) > 0) &&
@@ -161,9 +161,9 @@ MvFvbInitFvAndVariableStoreHeaders (
     (PcdGet32 (PcdFlashNvStorageFtwSpareSize) / BlockSize > 0));
 
   // Ensure the Variable areas are aligned on block size boundaries
-  ASSERT ((PcdGet32 (PcdFlashNvStorageVariableBase) % BlockSize) == 0);
-  ASSERT ((PcdGet32 (PcdFlashNvStorageFtwWorkingBase) % BlockSize) == 0);
-  ASSERT ((PcdGet32 (PcdFlashNvStorageFtwSpareBase) % BlockSize) == 0);
+  ASSERT ((PcdGet64 (PcdFlashNvStorageVariableBase64) % BlockSize) == 0);
+  ASSERT ((PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) % BlockSize) == 0);
+  ASSERT ((PcdGet64 (PcdFlashNvStorageFtwSpareBase64) % BlockSize) == 0);
 
   //
   // EFI_FIRMWARE_VOLUME_HEADER
@@ -1009,8 +1009,8 @@ MvFvbConfigureFlashInstance (
   }
 
   // Fill remaining flash description
-  FlashInstance->DeviceBaseAddress = PcdGet32 (PcdSpiMemoryBase);
-  FlashInstance->RegionBaseAddress = FixedPcdGet32 (PcdFlashNvStorageVariableBase);
+  FlashInstance->DeviceBaseAddress = PcdGet64 (PcdSpiMemoryBase);
+  FlashInstance->RegionBaseAddress = FixedPcdGet64 (PcdFlashNvStorageVariableBase64);
   FlashInstance->FvbOffset = FlashInstance->RegionBaseAddress -
                              FlashInstance->DeviceBaseAddress;
   FlashInstance->FvbSize = PcdGet32(PcdFlashNvStorageVariableSize) +
-- 
2.7.4


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