Series comparison

-[v7 0/5] Refactor capability search into common macros
+[v8 0/5] Refactor capability search into common macros
 . Refactor capability search into common macros.
 . Refactor capability search functions to eliminate code duplication.
 . DWC/CDNS use common PCI host bridge macros for finding the
    capabilities.
 . Use cdns_pcie_find_*capability to avoid hardcode.
+Changes since v7:
+- Patch 2/5 and 3/5 compilation error resolved.
+- Other patches are unchanged.
 Changes since v6:
 - Refactor capability search into common macros.
 - Delete pci-host-helpers.c and MAINTAINERS.
 ...
  .../pci/controller/cadence/pcie-cadence-ep.c  | 40 +++++----
  drivers/pci/controller/cadence/pcie-cadence.c | 28 +++++++
  drivers/pci/controller/cadence/pcie-cadence.h | 18 +++--
  drivers/pci/controller/dwc/pcie-designware.c  | 72 ++---------------
- drivers/pci/pci.c                             | 79 +++++-------------
+ drivers/pci/pci.c                             | 80 ++++++------------
  drivers/pci/pci.h                             | 81 +++++++++++++++++++
  include/uapi/linux/pci_regs.h                 |  2 +
-files changed, 176 insertions(+), 144 deletions(-)
+files changed, 177 insertions(+), 144 deletions(-)
 base-commit: acb4f33713b9f6cadb6143f211714c343465411c
 --
 .25.1

-[v7 1/5] PCI: Refactor capability search into common macros
+[v8 1/5] PCI: Refactor capability search into common macros
 Introduce PCI_FIND_NEXT_CAP_TTL and PCI_FIND_NEXT_EXT_CAPABILITY macros
 to consolidate duplicate PCI capability search logic found throughout the
 driver tree. This refactoring:
 . Eliminates code duplication in capability scanning routines
 . Provides a standardized, maintainable implementation
 . Reduces error-prone copy-paste implementations
 . Maintains identical functionality to existing code
 The macros abstract the low-level capability register scanning while
 preserving the existing PCI configuration space access patterns. They will
 enable future conversions of multiple capability search implementations
 across various drivers (e.g., PCI core, controller drivers) to use
 this centralized logic.
 Signed-off-by: Hans Zhang <18255117159@163.com>
 ---
  drivers/pci/pci.h             | 81 +++++++++++++++++++++++++++++++++++
  include/uapi/linux/pci_regs.h |  2 +
 files changed, 83 insertions(+)
 diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
 index XXXXXXX..XXXXXXX 100644
 --- a/drivers/pci/pci.h
 +++ b/drivers/pci/pci.h
 @@ -XXX,XX +XXX,XX @@ bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
  bool pcie_cap_has_lnkctl2(const struct pci_dev *dev);
  bool pcie_cap_has_rtctl(const struct pci_dev *dev);
 +/* Standard Capability finder */
 +/**
 + * PCI_FIND_NEXT_CAP_TTL - Find a PCI standard capability
 + * @read_cfg: Function pointer for reading PCI config space
 + * @start: Starting position to begin search
 + * @cap: Capability ID to find
 + * @args: Arguments to pass to read_cfg function
 + *
 + * Iterates through the capability list in PCI config space to find
 + * the specified capability. Implements TTL (time-to-live) protection
 + * against infinite loops.
 + *
 + * Returns: Position of the capability if found, 0 otherwise.
 + */
 +#define PCI_FIND_NEXT_CAP_TTL(read_cfg, start, cap, args...)        \
 +({                                    \
 +    u8 __pos = (start);                        \
 +    int __ttl = PCI_FIND_CAP_TTL;                    \
 +    u16 __ent;                            \
 +    u8 __found_pos = 0;                        \
 +    u8 __id;                            \
 +                                    \
 +    read_cfg(args, __pos, 1, (u32 *)&__pos);            \
 +                                    \
 +    while (__ttl--) {                        \
 +        if (__pos < PCI_STD_HEADER_SIZEOF)            \
 +            break;                        \
 +        __pos = ALIGN_DOWN(__pos, 4);                \
 +        read_cfg(args, __pos, 2, (u32 *)&__ent);        \
 +        __id = FIELD_GET(PCI_CAP_ID_MASK, __ent);        \
 +        if (__id == 0xff)                    \
 +            break;                        \
 +        if (__id == (cap)) {                    \
 +            __found_pos = __pos;                \
 +            break;                        \
 +        }                            \
 +        __pos = FIELD_GET(PCI_CAP_LIST_NEXT_MASK, __ent);    \
 +    }                                \
 +    __found_pos;                            \
 +})
 +
 +/* Extended Capability finder */
 +/**
 + * PCI_FIND_NEXT_EXT_CAPABILITY - Find a PCI extended capability
 + * @read_cfg: Function pointer for reading PCI config space
 + * @start: Starting position to begin search (0 for initial search)
 + * @cap: Extended capability ID to find
 + * @args: Arguments to pass to read_cfg function
 + *
 + * Searches the extended capability space in PCI config registers
 + * for the specified capability. Implements TTL protection against
 + * infinite loops using a calculated maximum search count.
 + *
 + * Returns: Position of the capability if found, 0 otherwise.
 + */
 +#define PCI_FIND_NEXT_EXT_CAPABILITY(read_cfg, start, cap, args...)        \
 +({                                        \
 +    u16 __pos = (start) ?: PCI_CFG_SPACE_SIZE;                \
 +    u16 __found_pos = 0;                            \
 +    int __ttl, __ret;                            \
 +    u32 __header;                                \
 +                                        \
 +    __ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;        \
 +    while (__ttl-- > 0 && __pos >= PCI_CFG_SPACE_SIZE) {            \
 +        __ret = read_cfg(args, __pos, 4, &__header);            \
 +        if (__ret != PCIBIOS_SUCCESSFUL)                \
 +            break;                            \
 +                                        \
 +        if (__header == 0)                        \
 +            break;                            \
 +                                        \
 +        if (PCI_EXT_CAP_ID(__header) == (cap) && __pos != start) {    \
 +            __found_pos = __pos;                    \
 +            break;                            \
 +        }                                \
 +                                        \
 +        __pos = PCI_EXT_CAP_NEXT(__header);                \
 +    }                                    \
 +    __found_pos;                                \
 +})
 +
  /* Functions internal to the PCI core code */
  #ifdef CONFIG_DMI
 diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/uapi/linux/pci_regs.h
 +++ b/include/uapi/linux/pci_regs.h
 @@ -XXX,XX +XXX,XX @@
  /* 0x48-0x7f reserved */
  /* Capability lists */
 +#define PCI_CAP_ID_MASK        0x00ff
 +#define PCI_CAP_LIST_NEXT_MASK    0xff00
  #define PCI_CAP_LIST_ID        0    /* Capability ID */
  #define  PCI_CAP_ID_PM        0x01    /* Power Management */
 --
 .25.1

-[v7 2/5] PCI: Refactor capability search functions to eliminate code duplication
+[v8 2/5] PCI: Refactor capability search functions to eliminate code duplication
 ...
 existing capability discovery patterns through thorough testing of PCI
 device enumeration and capability probing.
 Signed-off-by: Hans Zhang <18255117159@163.com>
 ---
- drivers/pci/pci.c | 79 +++++++++++++----------------------------------
+Changes since v7:
-file changed, 22 insertions(+), 57 deletions(-)
+https://lore.kernel.org/linux-pci/20250402042020.48681-3-18255117159@163.com
 - Resolve compilation errors.
 ---
  drivers/pci/pci.c | 80 ++++++++++++++---------------------------------
 file changed, 23 insertions(+), 57 deletions(-)
 diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
 index XXXXXXX..XXXXXXX 100644
 --- a/drivers/pci/pci.c
 +++ b/drivers/pci/pci.c
 ...
 @@ -XXX,XX +XXX,XX @@ EXPORT_SYMBOL_GPL(pci_get_dsn);
  static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
  {
 -    int rc, ttl = PCI_FIND_CAP_TTL;
++    int rc;
      u8 cap, mask;
      if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
 @@ -XXX,XX +XXX,XX @@ static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
          mask = HT_5BIT_CAP_MASK;
 ...

-[v7 3/5] PCI: dwc: Use common PCI host bridge APIs for finding the capabilities
+[v8 3/5] PCI: dwc: Use common PCI host bridge APIs for finding the capabilities
 Use the PCI core is now exposing generic macros for the host bridges to
 search for the PCIe capabilities, make use of them in the DWC driver.
 Signed-off-by: Hans Zhang <18255117159@163.com>
 ---
-Changes since v6:
+Changes since v7:
-https://lore.kernel.org/linux-pci/20250323164852.430546-3-18255117159@163.com/
+https://lore.kernel.org/linux-pci/20250402042020.48681-4-18255117159@163.com/
-- The patch commit message were modified.
+- Resolve compilation errors.
 Changes since v5:
 https://lore.kernel.org/linux-pci/20250321163803.391056-3-18255117159@163.com/
 - Kconfig add "select PCI_HOST_HELPERS"
 ---
  drivers/pci/controller/dwc/pcie-designware.c | 72 ++------------------
 file changed, 7 insertions(+), 65 deletions(-)
 diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
 ...
 -    reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
 -    next_cap_ptr = (reg & 0x00ff);
 -
 -    return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
 +    return PCI_FIND_NEXT_CAP_TTL(dw_pcie_read_cfg, PCI_CAPABILITY_LIST, cap,
-+                     pcie);
++                     pci);
  }
  EXPORT_SYMBOL_GPL(dw_pcie_find_capability);
 -static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start,
 -                        u8 cap)
 ...
 -}
 -
  u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap)
  {
 -    return dw_pcie_find_next_ext_capability(pci, 0, cap);
-+    return PCI_FIND_NEXT_EXT_CAPABILITY(dw_pcie_read_cfg, 0, cap, pcie);
++    return PCI_FIND_NEXT_EXT_CAPABILITY(dw_pcie_read_cfg, 0, cap, pci);
  }
  EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
 --
 .25.1

-[v7 4/5] PCI: cadence: Use common PCI host bridge APIs for finding the capabilities
+[v8 4/5] PCI: cadence: Use common PCI host bridge APIs for finding the capabilities
 Use the PCI core is now exposing generic macros for the host bridges to
 search for the PCIe capabilities, make use of them in the CDNS driver.
 Signed-off-by: Hans Zhang <18255117159@163.com>
 ---
 Changes since v6:
 https://lore.kernel.org/linux-pci/20250323164852.430546-4-18255117159@163.com/
 - The patch commit message were modified.
 Changes since v5:
 https://lore.kernel.org/linux-pci/20250321163803.391056-4-18255117159@163.com
 - Kconfig add "select PCI_HOST_HELPERS"
 ---
  drivers/pci/controller/cadence/pcie-cadence.c | 28 +++++++++++++++++++
  drivers/pci/controller/cadence/pcie-cadence.h | 13 +++++++++
 files changed, 41 insertions(+)
 diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c
 index XXXXXXX..XXXXXXX 100644
 --- a/drivers/pci/controller/cadence/pcie-cadence.c
 +++ b/drivers/pci/controller/cadence/pcie-cadence.c
 @@ -XXX,XX +XXX,XX @@
  #include <linux/of.h>
  #include "pcie-cadence.h"
 +#include "../../pci.h"
 +
 +static int cdns_pcie_read_cfg(void *priv, int where, int size, u32 *val)
 +{
 +    struct cdns_pcie *pcie = priv;
 +
 +    if (size == 4)
 +        *val = cdns_pcie_readl(pcie, where);
 +    else if (size == 2)
 +        *val = cdns_pcie_readw(pcie, where);
 +    else if (size == 1)
 +        *val = cdns_pcie_readb(pcie, where);
 +
 +    return PCIBIOS_SUCCESSFUL;
 +}
 +
 +u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap)
 +{
 +    return PCI_FIND_NEXT_CAP_TTL(cdns_pcie_read_cfg, PCI_CAPABILITY_LIST,
 +                     cap, pcie);
 +}
 +EXPORT_SYMBOL_GPL(cdns_pcie_find_capability);
 +
 +u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap)
 +{
 +    return PCI_FIND_NEXT_EXT_CAPABILITY(cdns_pcie_read_cfg, 0, cap, pcie);
 +}
 +EXPORT_SYMBOL_GPL(cdns_pcie_find_ext_capability);
  void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie)
  {
 diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
 index XXXXXXX..XXXXXXX 100644
 --- a/drivers/pci/controller/cadence/pcie-cadence.h
 +++ b/drivers/pci/controller/cadence/pcie-cadence.h
 @@ -XXX,XX +XXX,XX @@ static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg)
      return readl(pcie->reg_base + reg);
  }
 +static inline u32 cdns_pcie_readw(struct cdns_pcie *pcie, u32 reg)
 +{
 +    return readw(pcie->reg_base + reg);
 +}
 +
 +static inline u32 cdns_pcie_readb(struct cdns_pcie *pcie, u32 reg)
 +{
 +    return readb(pcie->reg_base + reg);
 +}
 +
  static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size)
  {
      void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4);
 @@ -XXX,XX +XXX,XX @@ static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
  }
  #endif
 +u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap);
 +u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap);
 +
  void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie);
  void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
 --
 .25.1

-[v7 5/5] PCI: cadence: Use cdns_pcie_find_*capability to avoid hardcode.
+[v8 5/5] PCI: cadence: Use cdns_pcie_find_*capability to avoid hardcode.
 ...
 This avoids hardcoding the offsets in the driver.
 Signed-off-by: Hans Zhang <18255117159@163.com>
 ---
-Changes since v5~v6:
+Changes since v5~v7:
 - None
 Changes since v4:
 https://lore.kernel.org/linux-pci/20250321101710.371480-5-18255117159@163.com/
 ...

1. Refactor capability search into common macros.
2. Refactor capability search functions to eliminate code duplication.
2. DWC/CDNS use common PCI host bridge macros for finding the
   capabilities.
3. Use cdns_pcie_find_*capability to avoid hardcode.

Changes since v6:
- Refactor capability search into common macros.
- Delete pci-host-helpers.c and MAINTAINERS.

Changes since v5:
- If you put the helpers in drivers/pci/pci.c, they unnecessarily enlarge
  the kernel's .text section even if it's known already at compile time
  that they're never going to be used (e.g. on x86).
- Move the API for find capabilitys to a new file called
  pci-host-helpers.c.
- Add new patch for MAINTAINERS.

Changes since v4:
- Resolved [v4 1/4] compilation warning.
- The patch subject and commit message were modified.

Changes since v3:
- Resolved [v3 1/4] compilation error.
- Other patches are not modified.

Changes since v2:
- Add and split into a series of patches.

Hans Zhang (5):
  PCI: Refactor capability search into common macros
  PCI: Refactor capability search functions to eliminate code
    duplication
  PCI: dwc: Use common PCI host bridge APIs for finding the capabilities
  PCI: cadence: Use common PCI host bridge APIs for finding the
    capabilities
  PCI: cadence: Use cdns_pcie_find_*capability to avoid hardcode.

.../pci/controller/cadence/pcie-cadence-ep.c  | 40 +++++----
 drivers/pci/controller/cadence/pcie-cadence.c | 28 +++++++
 drivers/pci/controller/cadence/pcie-cadence.h | 18 +++--
 drivers/pci/controller/dwc/pcie-designware.c  | 72 ++---------------
 drivers/pci/pci.c                             | 79 +++++-------------
 drivers/pci/pci.h                             | 81 +++++++++++++++++++
 include/uapi/linux/pci_regs.h                 |  2 +
 7 files changed, 176 insertions(+), 144 deletions(-)

base-commit: acb4f33713b9f6cadb6143f211714c343465411c
-- 
2.25.1

Introduce PCI_FIND_NEXT_CAP_TTL and PCI_FIND_NEXT_EXT_CAPABILITY macros
to consolidate duplicate PCI capability search logic found throughout the
driver tree. This refactoring:

1. Eliminates code duplication in capability scanning routines
  2. Provides a standardized, maintainable implementation
  3. Reduces error-prone copy-paste implementations
  4. Maintains identical functionality to existing code

The macros abstract the low-level capability register scanning while
preserving the existing PCI configuration space access patterns. They will
enable future conversions of multiple capability search implementations
across various drivers (e.g., PCI core, controller drivers) to use
this centralized logic.

Signed-off-by: Hans Zhang <18255117159@163.com>
---
 drivers/pci/pci.h             | 81 +++++++++++++++++++++++++++++++++++
 include/uapi/linux/pci_regs.h |  2 +
 2 files changed, 83 insertions(+)

diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index XXXXXXX..XXXXXXX 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -XXX,XX +XXX,XX @@ bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev);
 bool pcie_cap_has_rtctl(const struct pci_dev *dev);
 
+/* Standard Capability finder */
+/**
+ * PCI_FIND_NEXT_CAP_TTL - Find a PCI standard capability
+ * @read_cfg: Function pointer for reading PCI config space
+ * @start: Starting position to begin search
+ * @cap: Capability ID to find
+ * @args: Arguments to pass to read_cfg function
+ *
+ * Iterates through the capability list in PCI config space to find
+ * the specified capability. Implements TTL (time-to-live) protection
+ * against infinite loops.
+ *
+ * Returns: Position of the capability if found, 0 otherwise.
+ */
+#define PCI_FIND_NEXT_CAP_TTL(read_cfg, start, cap, args...)		\
+({									\
+	u8 __pos = (start);						\
+	int __ttl = PCI_FIND_CAP_TTL;					\
+	u16 __ent;							\
+	u8 __found_pos = 0;						\
+	u8 __id;							\
+									\
+	read_cfg(args, __pos, 1, (u32 *)&__pos);			\
+									\
+	while (__ttl--) {						\
+		if (__pos < PCI_STD_HEADER_SIZEOF)			\
+			break;						\
+		__pos = ALIGN_DOWN(__pos, 4);				\
+		read_cfg(args, __pos, 2, (u32 *)&__ent);		\
+		__id = FIELD_GET(PCI_CAP_ID_MASK, __ent);		\
+		if (__id == 0xff)					\
+			break;						\
+		if (__id == (cap)) {					\
+			__found_pos = __pos;				\
+			break;						\
+		}							\
+		__pos = FIELD_GET(PCI_CAP_LIST_NEXT_MASK, __ent);	\
+	}								\
+	__found_pos;							\
+})
+
+/* Extended Capability finder */
+/**
+ * PCI_FIND_NEXT_EXT_CAPABILITY - Find a PCI extended capability
+ * @read_cfg: Function pointer for reading PCI config space
+ * @start: Starting position to begin search (0 for initial search)
+ * @cap: Extended capability ID to find
+ * @args: Arguments to pass to read_cfg function
+ *
+ * Searches the extended capability space in PCI config registers
+ * for the specified capability. Implements TTL protection against
+ * infinite loops using a calculated maximum search count.
+ *
+ * Returns: Position of the capability if found, 0 otherwise.
+ */
+#define PCI_FIND_NEXT_EXT_CAPABILITY(read_cfg, start, cap, args...)		\
+({										\
+	u16 __pos = (start) ?: PCI_CFG_SPACE_SIZE;				\
+	u16 __found_pos = 0;							\
+	int __ttl, __ret;							\
+	u32 __header;								\
+										\
+	__ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;		\
+	while (__ttl-- > 0 && __pos >= PCI_CFG_SPACE_SIZE) {			\
+		__ret = read_cfg(args, __pos, 4, &__header);			\
+		if (__ret != PCIBIOS_SUCCESSFUL)				\
+			break;							\
+										\
+		if (__header == 0)						\
+			break;							\
+										\
+		if (PCI_EXT_CAP_ID(__header) == (cap) && __pos != start) {	\
+			__found_pos = __pos;					\
+			break;							\
+		}								\
+										\
+		__pos = PCI_EXT_CAP_NEXT(__header);				\
+	}									\
+	__found_pos;								\
+})
+
 /* Functions internal to the PCI core code */
 
 #ifdef CONFIG_DMI
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index XXXXXXX..XXXXXXX 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -XXX,XX +XXX,XX @@
 /* 0x48-0x7f reserved */
 
 /* Capability lists */
+#define PCI_CAP_ID_MASK		0x00ff
+#define PCI_CAP_LIST_NEXT_MASK	0xff00
 
 #define PCI_CAP_LIST_ID		0	/* Capability ID */
 #define  PCI_CAP_ID_PM		0x01	/* Power Management */
-- 
2.25.1

Refactor the PCI capability and extended capability search functions
by consolidating common code patterns into reusable macros
(PCI_FIND_NEXT_CAP_TTL and PCI_FIND_NEXT_EXT_CAPABILITY). The main
changes include:

1. Introducing a unified config space read helper (__pci_bus_read_config).
2. Removing duplicate search logic from __pci_find_next_cap_ttl and
   pci_find_next_ext_capability.
3. Implementing consistent capability discovery using the new macros.
4. Simplifying HyperTransport capability lookup by leveraging the
   refactored code.

The refactoring maintains existing functionality while reducing code
duplication and improving maintainability. By centralizing the search
logic, we achieve better code consistency and make future updates easier.

This change has been verified to maintain backward compatibility with
existing capability discovery patterns through thorough testing of PCI
device enumeration and capability probing.

Signed-off-by: Hans Zhang <18255117159@163.com>
---
 drivers/pci/pci.c | 79 +++++++++++++----------------------------------
 1 file changed, 22 insertions(+), 57 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index XXXXXXX..XXXXXXX 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -XXX,XX +XXX,XX @@ static int pci_dev_str_match(struct pci_dev *dev, const char *p,
 	return 1;
 }
 
-static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
-				  u8 pos, int cap, int *ttl)
+static int __pci_bus_read_config(void *priv, unsigned int devfn, int where,
+				 u32 size, u32 *val)
 {
-	u8 id;
-	u16 ent;
+	struct pci_bus *bus = priv;
+	int ret;
 
-	pci_bus_read_config_byte(bus, devfn, pos, &pos);
+	if (size == 1)
+		ret = pci_bus_read_config_byte(bus, devfn, where, (u8 *)val);
+	else if (size == 2)
+		ret = pci_bus_read_config_word(bus, devfn, where, (u16 *)val);
+	else
+		ret = pci_bus_read_config_dword(bus, devfn, where, val);
 
-	while ((*ttl)--) {
-		if (pos < 0x40)
-			break;
-		pos &= ~3;
-		pci_bus_read_config_word(bus, devfn, pos, &ent);
+	return ret;
+}
 
-		id = ent & 0xff;
-		if (id == 0xff)
-			break;
-		if (id == cap)
-			return pos;
-		pos = (ent >> 8);
-	}
-	return 0;
+static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
+				  u8 pos, int cap)
+{
+	return PCI_FIND_NEXT_CAP_TTL(__pci_bus_read_config, pos, cap, bus,
+				     devfn);
 }
 
 static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
 			      u8 pos, int cap)
 {
-	int ttl = PCI_FIND_CAP_TTL;
-
-	return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
+	return __pci_find_next_cap_ttl(bus, devfn, pos, cap);
 }
 
 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
@@ -XXX,XX +XXX,XX @@ EXPORT_SYMBOL(pci_bus_find_capability);
  */
 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap)
 {
-	u32 header;
-	int ttl;
-	u16 pos = PCI_CFG_SPACE_SIZE;
-
-	/* minimum 8 bytes per capability */
-	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
-
 	if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
 		return 0;
 
-	if (start)
-		pos = start;
-
-	if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
-		return 0;
-
-	/*
-	 * If we have no capabilities, this is indicated by cap ID,
-	 * cap version and next pointer all being 0.
-	 */
-	if (header == 0)
-		return 0;
-
-	while (ttl-- > 0) {
-		if (PCI_EXT_CAP_ID(header) == cap && pos != start)
-			return pos;
-
-		pos = PCI_EXT_CAP_NEXT(header);
-		if (pos < PCI_CFG_SPACE_SIZE)
-			break;
-
-		if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
-			break;
-	}
-
-	return 0;
+	return PCI_FIND_NEXT_EXT_CAPABILITY(__pci_bus_read_config, start, cap,
+					    dev->bus, dev->devfn);
 }
 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
 
@@ -XXX,XX +XXX,XX @@ EXPORT_SYMBOL_GPL(pci_get_dsn);
 
 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
 {
-	int rc, ttl = PCI_FIND_CAP_TTL;
 	u8 cap, mask;
 
 	if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
@@ -XXX,XX +XXX,XX @@ static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
 		mask = HT_5BIT_CAP_MASK;
 
 	pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
-				      PCI_CAP_ID_HT, &ttl);
+				      PCI_CAP_ID_HT);
 	while (pos) {
 		rc = pci_read_config_byte(dev, pos + 3, &cap);
 		if (rc != PCIBIOS_SUCCESSFUL)
@@ -XXX,XX +XXX,XX @@ static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
 
 		pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
 					      pos + PCI_CAP_LIST_NEXT,
-					      PCI_CAP_ID_HT, &ttl);
+					      PCI_CAP_ID_HT);
 	}
 
 	return 0;
-- 
2.25.1

Use the PCI core is now exposing generic macros for the host bridges to
search for the PCIe capabilities, make use of them in the DWC driver.

Signed-off-by: Hans Zhang <18255117159@163.com>
---
Changes since v6:
https://lore.kernel.org/linux-pci/20250323164852.430546-3-18255117159@163.com/

- The patch commit message were modified.

Changes since v5:
https://lore.kernel.org/linux-pci/20250321163803.391056-3-18255117159@163.com/

- Kconfig add "select PCI_HOST_HELPERS"
---
 drivers/pci/controller/dwc/pcie-designware.c | 72 ++------------------
 1 file changed, 7 insertions(+), 65 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index XXXXXXX..XXXXXXX 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -XXX,XX +XXX,XX @@ void dw_pcie_version_detect(struct dw_pcie *pci)
 		pci->type = ver;
 }
 
-/*
- * These interfaces resemble the pci_find_*capability() interfaces, but these
- * are for configuring host controllers, which are bridges *to* PCI devices but
- * are not PCI devices themselves.
- */
-static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
-				  u8 cap)
+static int dw_pcie_read_cfg(void *priv, int where, int size, u32 *val)
 {
-	u8 cap_id, next_cap_ptr;
-	u16 reg;
-
-	if (!cap_ptr)
-		return 0;
-
-	reg = dw_pcie_readw_dbi(pci, cap_ptr);
-	cap_id = (reg & 0x00ff);
-
-	if (cap_id > PCI_CAP_ID_MAX)
-		return 0;
+	struct dw_pcie *pcie = priv;
 
-	if (cap_id == cap)
-		return cap_ptr;
+	*val = dw_pcie_read_dbi(pcie, where, size);
 
-	next_cap_ptr = (reg & 0xff00) >> 8;
-	return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
+	return PCIBIOS_SUCCESSFUL;
 }
 
 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
 {
-	u8 next_cap_ptr;
-	u16 reg;
-
-	reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
-	next_cap_ptr = (reg & 0x00ff);
-
-	return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
+	return PCI_FIND_NEXT_CAP_TTL(dw_pcie_read_cfg, PCI_CAPABILITY_LIST, cap,
+				     pcie);
 }
 EXPORT_SYMBOL_GPL(dw_pcie_find_capability);
 
-static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start,
-					    u8 cap)
-{
-	u32 header;
-	int ttl;
-	int pos = PCI_CFG_SPACE_SIZE;
-
-	/* minimum 8 bytes per capability */
-	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
-
-	if (start)
-		pos = start;
-
-	header = dw_pcie_readl_dbi(pci, pos);
-	/*
-	 * If we have no capabilities, this is indicated by cap ID,
-	 * cap version and next pointer all being 0.
-	 */
-	if (header == 0)
-		return 0;
-
-	while (ttl-- > 0) {
-		if (PCI_EXT_CAP_ID(header) == cap && pos != start)
-			return pos;
-
-		pos = PCI_EXT_CAP_NEXT(header);
-		if (pos < PCI_CFG_SPACE_SIZE)
-			break;
-
-		header = dw_pcie_readl_dbi(pci, pos);
-	}
-
-	return 0;
-}
-
 u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap)
 {
-	return dw_pcie_find_next_ext_capability(pci, 0, cap);
+	return PCI_FIND_NEXT_EXT_CAPABILITY(dw_pcie_read_cfg, 0, cap, pcie);
 }
 EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
 
-- 
2.25.1

Use the PCI core is now exposing generic macros for the host bridges to
search for the PCIe capabilities, make use of them in the CDNS driver.

Signed-off-by: Hans Zhang <18255117159@163.com>
---
Changes since v6:
https://lore.kernel.org/linux-pci/20250323164852.430546-4-18255117159@163.com/

- The patch commit message were modified.

Changes since v5:
https://lore.kernel.org/linux-pci/20250321163803.391056-4-18255117159@163.com

- Kconfig add "select PCI_HOST_HELPERS"
---
 drivers/pci/controller/cadence/pcie-cadence.c | 28 +++++++++++++++++++
 drivers/pci/controller/cadence/pcie-cadence.h | 13 +++++++++
 2 files changed, 41 insertions(+)

diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c
index XXXXXXX..XXXXXXX 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.c
+++ b/drivers/pci/controller/cadence/pcie-cadence.c
@@ -XXX,XX +XXX,XX @@
 #include <linux/of.h>
 
 #include "pcie-cadence.h"
+#include "../../pci.h"
+
+static int cdns_pcie_read_cfg(void *priv, int where, int size, u32 *val)
+{
+	struct cdns_pcie *pcie = priv;
+
+	if (size == 4)
+		*val = cdns_pcie_readl(pcie, where);
+	else if (size == 2)
+		*val = cdns_pcie_readw(pcie, where);
+	else if (size == 1)
+		*val = cdns_pcie_readb(pcie, where);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap)
+{
+	return PCI_FIND_NEXT_CAP_TTL(cdns_pcie_read_cfg, PCI_CAPABILITY_LIST,
+				     cap, pcie);
+}
+EXPORT_SYMBOL_GPL(cdns_pcie_find_capability);
+
+u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap)
+{
+	return PCI_FIND_NEXT_EXT_CAPABILITY(cdns_pcie_read_cfg, 0, cap, pcie);
+}
+EXPORT_SYMBOL_GPL(cdns_pcie_find_ext_capability);
 
 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie)
 {
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index XXXXXXX..XXXXXXX 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -XXX,XX +XXX,XX @@ static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg)
 	return readl(pcie->reg_base + reg);
 }
 
+static inline u32 cdns_pcie_readw(struct cdns_pcie *pcie, u32 reg)
+{
+	return readw(pcie->reg_base + reg);
+}
+
+static inline u32 cdns_pcie_readb(struct cdns_pcie *pcie, u32 reg)
+{
+	return readb(pcie->reg_base + reg);
+}
+
 static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size)
 {
 	void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4);
@@ -XXX,XX +XXX,XX @@ static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
 }
 #endif
 
+u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap);
+u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap);
+
 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie);
 
 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
-- 
2.25.1

The PCIe capability/extended capability offsets are not guaranteed to be
the same across all SoCs integrating the Cadence PCIe IP. Hence, use the
cdns_pcie_find_{ext}_capability() APIs for finding them.

This avoids hardcoding the offsets in the driver.

Signed-off-by: Hans Zhang <18255117159@163.com>
---
Changes since v5~v6:

- None

Changes since v4:
https://lore.kernel.org/linux-pci/20250321101710.371480-5-18255117159@163.com/

- The patch subject and commit message were modified.
---
 .../pci/controller/cadence/pcie-cadence-ep.c  | 40 +++++++++++--------
 drivers/pci/controller/cadence/pcie-cadence.h |  5 ---
 2 files changed, 23 insertions(+), 22 deletions(-)

diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
index XXXXXXX..XXXXXXX 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
@@ -XXX,XX +XXX,XX @@
 
 static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn)
 {
-	u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET;
 	u32 first_vf_offset, stride;
+	u16 cap;
 
 	if (vfn == 0)
 		return fn;
 
+	cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV);
 	first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OFFSET);
 	stride = cdns_pcie_ep_fn_readw(pcie, fn, cap +  PCI_SRIOV_VF_STRIDE);
 	fn = fn + first_vf_offset + ((vfn - 1) * stride);
@@ -XXX,XX +XXX,XX @@ static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn,
 				     struct pci_epf_header *hdr)
 {
 	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
-	u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET;
 	struct cdns_pcie *pcie = &ep->pcie;
 	u32 reg;
+	u16 cap;
 
+	cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV);
 	if (vfn > 1) {
 		dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n");
 		return -EINVAL;
@@ -XXX,XX +XXX,XX @@ static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 mmc)
 {
 	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
 	struct cdns_pcie *pcie = &ep->pcie;
-	u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
 	u16 flags;
+	u8 cap;
 
+	cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI);
 	fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);
 
 	/*
@@ -XXX,XX +XXX,XX @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn)
 {
 	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
 	struct cdns_pcie *pcie = &ep->pcie;
-	u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
 	u16 flags, mme;
+	u8 cap;
 
+	cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI);
 	fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);
 
 	/* Validate that the MSI feature is actually enabled. */
@@ -XXX,XX +XXX,XX @@ static int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
 {
 	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
 	struct cdns_pcie *pcie = &ep->pcie;
-	u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET;
 	u32 val, reg;
+	u8 cap;
 
+	cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX);
 	func_no = cdns_pcie_get_fn_from_vfn(pcie, func_no, vfunc_no);
 
 	reg = cap + PCI_MSIX_FLAGS;
@@ -XXX,XX +XXX,XX @@ static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn,
 {
 	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
 	struct cdns_pcie *pcie = &ep->pcie;
-	u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET;
 	u32 val, reg;
+	u8 cap;
 
+	cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX);
 	fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);
 
 	reg = cap + PCI_MSIX_FLAGS;
@@ -XXX,XX +XXX,XX @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn,
 				     u8 interrupt_num)
 {
 	struct cdns_pcie *pcie = &ep->pcie;
-	u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
 	u16 flags, mme, data, data_mask;
-	u8 msi_count;
 	u64 pci_addr, pci_addr_mask = 0xff;
+	u8 msi_count, cap;
 
+	cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI);
 	fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);
 
 	/* Check whether the MSI feature has been enabled by the PCI host. */
@@ -XXX,XX +XXX,XX @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn,
 				    u32 *msi_addr_offset)
 {
 	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
-	u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
 	struct cdns_pcie *pcie = &ep->pcie;
 	u64 pci_addr, pci_addr_mask = 0xff;
 	u16 flags, mme, data, data_mask;
-	u8 msi_count;
+	u8 msi_count, cap;
 	int ret;
 	int i;
 
+	cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI);
 	fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);
 
 	/* Check whether the MSI feature has been enabled by the PCI host. */
@@ -XXX,XX +XXX,XX @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn,
 static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn,
 				      u16 interrupt_num)
 {
-	u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET;
 	u32 tbl_offset, msg_data, reg;
 	struct cdns_pcie *pcie = &ep->pcie;
 	struct pci_epf_msix_tbl *msix_tbl;
 	struct cdns_pcie_epf *epf;
 	u64 pci_addr_mask = 0xff;
 	u64 msg_addr;
+	u8 bir, cap;
 	u16 flags;
-	u8 bir;
 
+	cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX);
 	epf = &ep->epf[fn];
 	if (vfn > 0)
 		epf = &epf->epf[vfn - 1];
@@ -XXX,XX +XXX,XX @@ static int cdns_pcie_ep_start(struct pci_epc *epc)
 	int max_epfs = sizeof(epc->function_num_map) * 8;
 	int ret, epf, last_fn;
 	u32 reg, value;
+	u8 cap;
 
+	cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_EXP);
 	/*
 	 * BIT(0) is hardwired to 1, hence function 0 is always enabled
 	 * and can't be disabled anyway.
@@ -XXX,XX +XXX,XX @@ static int cdns_pcie_ep_start(struct pci_epc *epc)
 				continue;
 
 			value = cdns_pcie_ep_fn_readl(pcie, epf,
-					CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET +
-					PCI_EXP_DEVCAP);
+						      cap + PCI_EXP_DEVCAP);
 			value &= ~PCI_EXP_DEVCAP_FLR;
-			cdns_pcie_ep_fn_writel(pcie, epf,
-					CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET +
-					PCI_EXP_DEVCAP, value);
+			cdns_pcie_ep_fn_writel(pcie, epf, cap + PCI_EXP_DEVCAP,
+					       value);
 		}
 	}
 
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index XXXXXXX..XXXXXXX 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -XXX,XX +XXX,XX @@
  */
 #define CDNS_PCIE_EP_FUNC_BASE(fn)	(((fn) << 12) & GENMASK(19, 12))
 
-#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET	0x90
-#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET	0xb0
-#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET	0xc0
-#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET	0x200
-
 /*
  * Endpoint PF Registers
  */
-- 
2.25.1

Changes since v7:
- Patch 2/5 and 3/5 compilation error resolved.
- Other patches are unchanged.

Changes since v6:
- Refactor capability search into common macros.
- Delete pci-host-helpers.c and MAINTAINERS.

Changes since v4:
- Resolved [v4 1/4] compilation warning.
- The patch subject and commit message were modified.

Changes since v3:
- Resolved [v3 1/4] compilation error.
- Other patches are not modified.

Changes since v2:
- Add and split into a series of patches.

.../pci/controller/cadence/pcie-cadence-ep.c  | 40 +++++----
 drivers/pci/controller/cadence/pcie-cadence.c | 28 +++++++
 drivers/pci/controller/cadence/pcie-cadence.h | 18 +++--
 drivers/pci/controller/dwc/pcie-designware.c  | 72 ++---------------
 drivers/pci/pci.c                             | 80 ++++++------------
 drivers/pci/pci.h                             | 81 +++++++++++++++++++
 include/uapi/linux/pci_regs.h                 |  2 +
 7 files changed, 177 insertions(+), 144 deletions(-)

base-commit: acb4f33713b9f6cadb6143f211714c343465411c
-- 
2.25.1

Introduce PCI_FIND_NEXT_CAP_TTL and PCI_FIND_NEXT_EXT_CAPABILITY macros
to consolidate duplicate PCI capability search logic found throughout the
driver tree. This refactoring:

Signed-off-by: Hans Zhang <18255117159@163.com>
---
 drivers/pci/pci.h             | 81 +++++++++++++++++++++++++++++++++++
 include/uapi/linux/pci_regs.h |  2 +
 2 files changed, 83 insertions(+)

This change has been verified to maintain backward compatibility with
existing capability discovery patterns through thorough testing of PCI
device enumeration and capability probing.

Signed-off-by: Hans Zhang <18255117159@163.com>
---
Changes since v7:
https://lore.kernel.org/linux-pci/20250402042020.48681-3-18255117159@163.com

- Resolve compilation errors.
---
 drivers/pci/pci.c | 80 ++++++++++++++---------------------------------
 1 file changed, 23 insertions(+), 57 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index XXXXXXX..XXXXXXX 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -XXX,XX +XXX,XX @@ static int pci_dev_str_match(struct pci_dev *dev, const char *p,
 	return 1;
 }
 
-static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
-				  u8 pos, int cap, int *ttl)
+static int __pci_bus_read_config(void *priv, unsigned int devfn, int where,
+				 u32 size, u32 *val)
 {
-	u8 id;
-	u16 ent;
+	struct pci_bus *bus = priv;
+	int ret;
 
-	pci_bus_read_config_byte(bus, devfn, pos, &pos);
+	if (size == 1)
+		ret = pci_bus_read_config_byte(bus, devfn, where, (u8 *)val);
+	else if (size == 2)
+		ret = pci_bus_read_config_word(bus, devfn, where, (u16 *)val);
+	else
+		ret = pci_bus_read_config_dword(bus, devfn, where, val);
 
-	while ((*ttl)--) {
-		if (pos < 0x40)
-			break;
-		pos &= ~3;
-		pci_bus_read_config_word(bus, devfn, pos, &ent);
+	return ret;
+}
 
-		id = ent & 0xff;
-		if (id == 0xff)
-			break;
-		if (id == cap)
-			return pos;
-		pos = (ent >> 8);
-	}
-	return 0;
+static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
+				  u8 pos, int cap)
+{
+	return PCI_FIND_NEXT_CAP_TTL(__pci_bus_read_config, pos, cap, bus,
+				     devfn);
 }
 
 static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
 			      u8 pos, int cap)
 {
-	int ttl = PCI_FIND_CAP_TTL;
-
-	return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
+	return __pci_find_next_cap_ttl(bus, devfn, pos, cap);
 }
 
 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
@@ -XXX,XX +XXX,XX @@ EXPORT_SYMBOL(pci_bus_find_capability);
  */
 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap)
 {
-	u32 header;
-	int ttl;
-	u16 pos = PCI_CFG_SPACE_SIZE;
-
-	/* minimum 8 bytes per capability */
-	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
-
 	if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
 		return 0;
 
-	if (start)
-		pos = start;
-
-	if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
-		return 0;
-
-	/*
-	 * If we have no capabilities, this is indicated by cap ID,
-	 * cap version and next pointer all being 0.
-	 */
-	if (header == 0)
-		return 0;
-
-	while (ttl-- > 0) {
-		if (PCI_EXT_CAP_ID(header) == cap && pos != start)
-			return pos;
-
-		pos = PCI_EXT_CAP_NEXT(header);
-		if (pos < PCI_CFG_SPACE_SIZE)
-			break;
-
-		if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
-			break;
-	}
-
-	return 0;
+	return PCI_FIND_NEXT_EXT_CAPABILITY(__pci_bus_read_config, start, cap,
+					    dev->bus, dev->devfn);
 }
 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
 
@@ -XXX,XX +XXX,XX @@ EXPORT_SYMBOL_GPL(pci_get_dsn);
 
 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
 {
-	int rc, ttl = PCI_FIND_CAP_TTL;
+	int rc;
 	u8 cap, mask;
 
 	if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
@@ -XXX,XX +XXX,XX @@ static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
 		mask = HT_5BIT_CAP_MASK;
 
 	pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
-				      PCI_CAP_ID_HT, &ttl);
+				      PCI_CAP_ID_HT);
 	while (pos) {
 		rc = pci_read_config_byte(dev, pos + 3, &cap);
 		if (rc != PCIBIOS_SUCCESSFUL)
@@ -XXX,XX +XXX,XX @@ static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
 
 		pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
 					      pos + PCI_CAP_LIST_NEXT,
-					      PCI_CAP_ID_HT, &ttl);
+					      PCI_CAP_ID_HT);
 	}
 
 	return 0;
-- 
2.25.1

Use the PCI core is now exposing generic macros for the host bridges to
search for the PCIe capabilities, make use of them in the DWC driver.

Signed-off-by: Hans Zhang <18255117159@163.com>
---
Changes since v7:
https://lore.kernel.org/linux-pci/20250402042020.48681-4-18255117159@163.com/

- Resolve compilation errors.
---
 drivers/pci/controller/dwc/pcie-designware.c | 72 ++------------------
 1 file changed, 7 insertions(+), 65 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index XXXXXXX..XXXXXXX 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -XXX,XX +XXX,XX @@ void dw_pcie_version_detect(struct dw_pcie *pci)
 		pci->type = ver;
 }
 
-/*
- * These interfaces resemble the pci_find_*capability() interfaces, but these
- * are for configuring host controllers, which are bridges *to* PCI devices but
- * are not PCI devices themselves.
- */
-static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
-				  u8 cap)
+static int dw_pcie_read_cfg(void *priv, int where, int size, u32 *val)
 {
-	u8 cap_id, next_cap_ptr;
-	u16 reg;
-
-	if (!cap_ptr)
-		return 0;
-
-	reg = dw_pcie_readw_dbi(pci, cap_ptr);
-	cap_id = (reg & 0x00ff);
-
-	if (cap_id > PCI_CAP_ID_MAX)
-		return 0;
+	struct dw_pcie *pcie = priv;
 
-	if (cap_id == cap)
-		return cap_ptr;
+	*val = dw_pcie_read_dbi(pcie, where, size);
 
-	next_cap_ptr = (reg & 0xff00) >> 8;
-	return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
+	return PCIBIOS_SUCCESSFUL;
 }
 
 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
 {
-	u8 next_cap_ptr;
-	u16 reg;
-
-	reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
-	next_cap_ptr = (reg & 0x00ff);
-
-	return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
+	return PCI_FIND_NEXT_CAP_TTL(dw_pcie_read_cfg, PCI_CAPABILITY_LIST, cap,
+				     pci);
 }
 EXPORT_SYMBOL_GPL(dw_pcie_find_capability);
 
-static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start,
-					    u8 cap)
-{
-	u32 header;
-	int ttl;
-	int pos = PCI_CFG_SPACE_SIZE;
-
-	/* minimum 8 bytes per capability */
-	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
-
-	if (start)
-		pos = start;
-
-	header = dw_pcie_readl_dbi(pci, pos);
-	/*
-	 * If we have no capabilities, this is indicated by cap ID,
-	 * cap version and next pointer all being 0.
-	 */
-	if (header == 0)
-		return 0;
-
-	while (ttl-- > 0) {
-		if (PCI_EXT_CAP_ID(header) == cap && pos != start)
-			return pos;
-
-		pos = PCI_EXT_CAP_NEXT(header);
-		if (pos < PCI_CFG_SPACE_SIZE)
-			break;
-
-		header = dw_pcie_readl_dbi(pci, pos);
-	}
-
-	return 0;
-}
-
 u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap)
 {
-	return dw_pcie_find_next_ext_capability(pci, 0, cap);
+	return PCI_FIND_NEXT_EXT_CAPABILITY(dw_pcie_read_cfg, 0, cap, pci);
 }
 EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
 
-- 
2.25.1

Use the PCI core is now exposing generic macros for the host bridges to
search for the PCIe capabilities, make use of them in the CDNS driver.

Signed-off-by: Hans Zhang <18255117159@163.com>
---
Changes since v6:
https://lore.kernel.org/linux-pci/20250323164852.430546-4-18255117159@163.com/

- The patch commit message were modified.

Changes since v5:
https://lore.kernel.org/linux-pci/20250321163803.391056-4-18255117159@163.com

This avoids hardcoding the offsets in the driver.

Signed-off-by: Hans Zhang <18255117159@163.com>
---
Changes since v5~v7:

- None

Changes since v4:
https://lore.kernel.org/linux-pci/20250321101710.371480-5-18255117159@163.com/