Pass PHY driver pointer to .match_phy_device OP in addition to phydev.

Having access to the PHY driver struct might be useful to check the

PHY ID of the driver is being matched for in case the PHY ID scanned in

the phydev is not consistent.

A scenario for this is a PHY that change PHY ID after a firmware is

loaded, in such case, the PHY ID stored in PHY device struct is not

valid anymore and PHY will manually scan the ID in the match_phy_device

function.

Having the PHY driver info is also useful for those PHY driver that

implement multiple simple .match_phy_device OP to match specific MMD PHY

ID. With this extra info if the parsing logic is the same, the matching

function can be generalized by using the phy_id in the PHY driver

instead of hardcoding.

Suggested-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>

Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

---

drivers/net/phy/bcm87xx.c | 6 ++++--

drivers/net/phy/icplus.c | 6 ++++--

drivers/net/phy/marvell10g.c | 12 ++++++++----

drivers/net/phy/micrel.c | 6 ++++--

drivers/net/phy/nxp-c45-tja11xx.c | 12 ++++++++----

drivers/net/phy/nxp-tja11xx.c | 6 ++++--

drivers/net/phy/phy_device.c | 2 +-

drivers/net/phy/realtek/realtek_main.c | 27 +++++++++++++++++---------

drivers/net/phy/teranetics.c | 3 ++-

include/linux/phy.h | 3 ++-

10 files changed, 55 insertions(+), 28 deletions(-)

diff --git a/drivers/net/phy/bcm87xx.c b/drivers/net/phy/bcm87xx.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/net/phy/bcm87xx.c

+++ b/drivers/net/phy/bcm87xx.c

@@ -XXX,XX +XXX,XX @@ static irqreturn_t bcm87xx_handle_interrupt(struct phy_device *phydev)

    return IRQ_HANDLED;

}

-static int bcm8706_match_phy_device(struct phy_device *phydev)

+static int bcm8706_match_phy_device(struct phy_device *phydev,

+                 const struct phy_driver *phydrv)

{

    return phydev->c45_ids.device_ids[4] == PHY_ID_BCM8706;

}

-static int bcm8727_match_phy_device(struct phy_device *phydev)

+static int bcm8727_match_phy_device(struct phy_device *phydev,

+                 const struct phy_driver *phydrv)

{

    return phydev->c45_ids.device_ids[4] == PHY_ID_BCM8727;

}

diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/net/phy/icplus.c

+++ b/drivers/net/phy/icplus.c

@@ -XXX,XX +XXX,XX @@ static int ip101a_g_match_phy_device(struct phy_device *phydev, bool ip101a)

    return ip101a == !ret;

}

-static int ip101a_match_phy_device(struct phy_device *phydev)

+static int ip101a_match_phy_device(struct phy_device *phydev,

+                 const struct phy_driver *phydrv)

{

    return ip101a_g_match_phy_device(phydev, true);

}

-static int ip101g_match_phy_device(struct phy_device *phydev)

+static int ip101g_match_phy_device(struct phy_device *phydev,

+                 const struct phy_driver *phydrv)

{

    return ip101a_g_match_phy_device(phydev, false);

}

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/net/phy/marvell10g.c

+++ b/drivers/net/phy/marvell10g.c

@@ -XXX,XX +XXX,XX @@ static int mv3310_get_number_of_ports(struct phy_device *phydev)

    return ret + 1;

}

-static int mv3310_match_phy_device(struct phy_device *phydev)

+static int mv3310_match_phy_device(struct phy_device *phydev,

+                 const struct phy_driver *phydrv)

{

    if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &

     MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310)

@@ -XXX,XX +XXX,XX @@ static int mv3310_match_phy_device(struct phy_device *phydev)

    return mv3310_get_number_of_ports(phydev) == 1;

}

-static int mv3340_match_phy_device(struct phy_device *phydev)

+static int mv3340_match_phy_device(struct phy_device *phydev,

+                 const struct phy_driver *phydrv)

{

    if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &

     MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310)

@@ -XXX,XX +XXX,XX @@ static int mv211x_match_phy_device(struct phy_device *phydev, bool has_5g)

    return !!(val & MDIO_PCS_SPEED_5G) == has_5g;

}

-static int mv2110_match_phy_device(struct phy_device *phydev)

+static int mv2110_match_phy_device(struct phy_device *phydev,

+                 const struct phy_driver *phydrv)

{

    return mv211x_match_phy_device(phydev, true);

}

-static int mv2111_match_phy_device(struct phy_device *phydev)

+static int mv2111_match_phy_device(struct phy_device *phydev,

+                 const struct phy_driver *phydrv)

{

    return mv211x_match_phy_device(phydev, false);

}

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/net/phy/micrel.c

+++ b/drivers/net/phy/micrel.c

@@ -XXX,XX +XXX,XX @@ static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,

        return !ret;

}

-static int ksz8051_match_phy_device(struct phy_device *phydev)

+static int ksz8051_match_phy_device(struct phy_device *phydev,

+                 const struct phy_driver *phydrv)

{

    return ksz8051_ksz8795_match_phy_device(phydev, true);

}

@@ -XXX,XX +XXX,XX @@ static int ksz8061_config_init(struct phy_device *phydev)

    return kszphy_config_init(phydev);

}

-static int ksz8795_match_phy_device(struct phy_device *phydev)

+static int ksz8795_match_phy_device(struct phy_device *phydev,

+                 const struct phy_driver *phydrv)

{

    return ksz8051_ksz8795_match_phy_device(phydev, false);

}

diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/net/phy/nxp-c45-tja11xx.c

+++ b/drivers/net/phy/nxp-c45-tja11xx.c

@@ -XXX,XX +XXX,XX @@ static int nxp_c45_macsec_ability(struct phy_device *phydev)

    return macsec_ability;

}

-static int tja1103_match_phy_device(struct phy_device *phydev)

+static int tja1103_match_phy_device(struct phy_device *phydev,

+                 const struct phy_driver *phydrv)

{

    return phy_id_compare(phydev->phy_id, PHY_ID_TJA_1103, PHY_ID_MASK) &&

     !nxp_c45_macsec_ability(phydev);

}

-static int tja1104_match_phy_device(struct phy_device *phydev)

+static int tja1104_match_phy_device(struct phy_device *phydev,

+                 const struct phy_driver *phydrv)

{

    return phy_id_compare(phydev->phy_id, PHY_ID_TJA_1103, PHY_ID_MASK) &&

     nxp_c45_macsec_ability(phydev);

}

-static int tja1120_match_phy_device(struct phy_device *phydev)

+static int tja1120_match_phy_device(struct phy_device *phydev,

+                 const struct phy_driver *phydrv)

{

    return phy_id_compare(phydev->phy_id, PHY_ID_TJA_1120, PHY_ID_MASK) &&

     !nxp_c45_macsec_ability(phydev);

}

-static int tja1121_match_phy_device(struct phy_device *phydev)

+static int tja1121_match_phy_device(struct phy_device *phydev,

+                 const struct phy_driver *phydrv)

{

    return phy_id_compare(phydev->phy_id, PHY_ID_TJA_1120, PHY_ID_MASK) &&

     nxp_c45_macsec_ability(phydev);

diff --git a/drivers/net/phy/nxp-tja11xx.c b/drivers/net/phy/nxp-tja11xx.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/net/phy/nxp-tja11xx.c

+++ b/drivers/net/phy/nxp-tja11xx.c

@@ -XXX,XX +XXX,XX @@ static int tja1102_match_phy_device(struct phy_device *phydev, bool port0)

    return !ret;

}

-static int tja1102_p0_match_phy_device(struct phy_device *phydev)

+static int tja1102_p0_match_phy_device(struct phy_device *phydev,

+                 const struct phy_driver *phydrv)

{

    return tja1102_match_phy_device(phydev, true);

}

-static int tja1102_p1_match_phy_device(struct phy_device *phydev)

+static int tja1102_p1_match_phy_device(struct phy_device *phydev,

+                 const struct phy_driver *phydrv)

{

    return tja1102_match_phy_device(phydev, false);

}

diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/net/phy/phy_device.c

+++ b/drivers/net/phy/phy_device.c

@@ -XXX,XX +XXX,XX @@ static int phy_bus_match(struct device *dev, const struct device_driver *drv)

        return 0;

    if (phydrv->match_phy_device)

-        return phydrv->match_phy_device(phydev);

+        return phydrv->match_phy_device(phydev, phydrv);

    if (phydev->is_c45) {

        for (i = 1; i < num_ids; i++) {

diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realtek/realtek_main.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/net/phy/realtek/realtek_main.c

+++ b/drivers/net/phy/realtek/realtek_main.c

@@ -XXX,XX +XXX,XX @@ static bool rtlgen_supports_mmd(struct phy_device *phydev)

    return val > 0;

}

-static int rtlgen_match_phy_device(struct phy_device *phydev)

+static int rtlgen_match_phy_device(struct phy_device *phydev,

+                 const struct phy_driver *phydrv)

{

    return phydev->phy_id == RTL_GENERIC_PHYID &&

     !rtlgen_supports_2_5gbps(phydev);

}

-static int rtl8226_match_phy_device(struct phy_device *phydev)

+static int rtl8226_match_phy_device(struct phy_device *phydev,

+                 const struct phy_driver *phydrv)

{

    return phydev->phy_id == RTL_GENERIC_PHYID &&

     rtlgen_supports_2_5gbps(phydev) &&

@@ -XXX,XX +XXX,XX @@ static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,

        return !is_c45 && (id == phydev->phy_id);

}

-static int rtl8221b_match_phy_device(struct phy_device *phydev)

+static int rtl8221b_match_phy_device(struct phy_device *phydev,

+                 const struct phy_driver *phydrv)

{

    return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev);

}

-static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev)

+static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev,

+                     const struct phy_driver *phydrv)

{

    return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false);

}

-static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev)

+static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev,

+                     const struct phy_driver *phydrv)

{

    return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true);

}

-static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev)

+static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev,

+                     const struct phy_driver *phydrv)

{

    return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false);

}

-static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev)

+static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev,

+                     const struct phy_driver *phydrv)

{

    return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true);

}

-static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev)

+static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev,

+                        const struct phy_driver *phydrv)

{

    if (phydev->is_c45)

        return false;

@@ -XXX,XX +XXX,XX @@ static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev)

    return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev);

}

-static int rtl8251b_c45_match_phy_device(struct phy_device *phydev)

+static int rtl8251b_c45_match_phy_device(struct phy_device *phydev,

+                     const struct phy_driver *phydrv)

{

    return rtlgen_is_c45_match(phydev, RTL_8251B, true);

}

diff --git a/drivers/net/phy/teranetics.c b/drivers/net/phy/teranetics.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/net/phy/teranetics.c

+++ b/drivers/net/phy/teranetics.c

@@ -XXX,XX +XXX,XX @@ static int teranetics_read_status(struct phy_device *phydev)

    return 0;

}

-static int teranetics_match_phy_device(struct phy_device *phydev)

+static int teranetics_match_phy_device(struct phy_device *phydev,

+                 const struct phy_driver *phydrv)

{

    return phydev->c45_ids.device_ids[3] == PHY_ID_TN2020;

}

diff --git a/include/linux/phy.h b/include/linux/phy.h

index XXXXXXX..XXXXXXX 100644

--- a/include/linux/phy.h

+++ b/include/linux/phy.h

@@ -XXX,XX +XXX,XX @@ struct phy_driver {

     * driver for the given phydev.     If NULL, matching is based on

     * phy_id and phy_id_mask.

     */

-    int (*match_phy_device)(struct phy_device *phydev);

+    int (*match_phy_device)(struct phy_device *phydev,

+                const struct phy_driver *phydrv);

    /**

     * @set_wol: Some devices (e.g. qnap TS-119P II) require PHY

--

2.48.1

Simplify .match_phy_device OP by using a generic function and using the

new phy_id PHY driver info instead of hardcoding the matching PHY ID.

Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

---

drivers/net/phy/bcm87xx.c | 14 ++++----------

1 file changed, 4 insertions(+), 10 deletions(-)

diff --git a/drivers/net/phy/bcm87xx.c b/drivers/net/phy/bcm87xx.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/net/phy/bcm87xx.c

+++ b/drivers/net/phy/bcm87xx.c

@@ -XXX,XX +XXX,XX @@ static irqreturn_t bcm87xx_handle_interrupt(struct phy_device *phydev)

    return IRQ_HANDLED;

}

-static int bcm8706_match_phy_device(struct phy_device *phydev,

+static int bcm87xx_match_phy_device(struct phy_device *phydev,

                 const struct phy_driver *phydrv)

{

-    return phydev->c45_ids.device_ids[4] == PHY_ID_BCM8706;

-}

-

-static int bcm8727_match_phy_device(struct phy_device *phydev,

-                 const struct phy_driver *phydrv)

-{

-    return phydev->c45_ids.device_ids[4] == PHY_ID_BCM8727;

+    return phydev->c45_ids.device_ids[4] == phydrv->phy_id;

}

static struct phy_driver bcm87xx_driver[] = {

@@ -XXX,XX +XXX,XX @@ static struct phy_driver bcm87xx_driver[] = {

    .read_status    = bcm87xx_read_status,

    .config_intr    = bcm87xx_config_intr,

    .handle_interrupt = bcm87xx_handle_interrupt,

-    .match_phy_device = bcm8706_match_phy_device,

+    .match_phy_device = bcm87xx_match_phy_device,

}, {

    .phy_id        = PHY_ID_BCM8727,

    .phy_id_mask    = 0xffffffff,

@@ -XXX,XX +XXX,XX @@ static struct phy_driver bcm87xx_driver[] = {

    .read_status    = bcm87xx_read_status,

    .config_intr    = bcm87xx_config_intr,

    .handle_interrupt = bcm87xx_handle_interrupt,

-    .match_phy_device = bcm8727_match_phy_device,

+    .match_phy_device = bcm87xx_match_phy_device,

} };

module_phy_driver(bcm87xx_driver);

--

2.48.1

Add support for Aeonsemi AS21xxx 10G C45 PHYs. These PHYs integrate

an IPC to setup some configuration and require special handling to

sync with the parity bit. The parity bit is a way the IPC use to

follow correct order of command sent.

Supported PHYs AS21011JB1, AS21011PB1, AS21010JB1, AS21010PB1,

AS21511JB1, AS21511PB1, AS21510JB1, AS21510PB1, AS21210JB1,

AS21210PB1 that all register with the PHY ID 0x7500 0x7510

before the firmware is loaded.

They all support up to 5 LEDs with various HW mode supported.

While implementing it was found some strange coincidence with using the

same logic for implementing C22 in MMD regs in Broadcom PHYs.

For reference here the AS21xxx PHY name logic:

AS21x1xxB1

^ ^^

| |J: Supports SyncE/PTP

| |P: No SyncE/PTP support

| 1: Supports 2nd Serdes

| 2: Not 2nd Serdes support

0: 10G, 5G, 2.5G

5: 5G, 2.5G

2: 2.5G

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

---

MAINTAINERS | 6 +

drivers/net/phy/Kconfig | 12 +

drivers/net/phy/Makefile | 1 +

drivers/net/phy/as21xxx.c | 1067 +++++++++++++++++++++++++++++++++++++

4 files changed, 1086 insertions(+)

create mode 100644 drivers/net/phy/as21xxx.c

diff --git a/MAINTAINERS b/MAINTAINERS

index XXXXXXX..XXXXXXX 100644

--- a/MAINTAINERS

+++ b/MAINTAINERS

@@ -XXX,XX +XXX,XX @@ F:    drivers/iio/accel/adxl380.h

F:    drivers/iio/accel/adxl380_i2c.c

F:    drivers/iio/accel/adxl380_spi.c

+AEONSEMI PHY DRIVER

+M:    Christian Marangi <ansuelsmth@gmail.com>

+L:    netdev@vger.kernel.org

+S:    Maintained

+F:    drivers/net/phy/as21xxx.c

+

AF8133J THREE-AXIS MAGNETOMETER DRIVER

M:    Ondřej Jirman <megi@xff.cz>

S:    Maintained

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig

index XXXXXXX..XXXXXXX 100644

--- a/drivers/net/phy/Kconfig

+++ b/drivers/net/phy/Kconfig

@@ -XXX,XX +XXX,XX @@ config AMCC_QT2025_PHY

    help

     Adds support for the Applied Micro Circuits Corporation QT2025 PHY.

+config AS21XXX_PHY

+    tristate "Aeonsemi AS21xxx PHYs"

+    help

+     Currently supports the Aeonsemi AS21xxx PHY.

+

+     These are C45 PHYs 10G that require all a generic firmware.

+

+     Supported PHYs AS21011JB1, AS21011PB1, AS21010JB1, AS21010PB1,

+     AS21511JB1, AS21511PB1, AS21510JB1, AS21510PB1, AS21210JB1,

+     AS21210PB1 that all register with the PHY ID 0x7500 0x7500

+     before the firmware is loaded.

+

source "drivers/net/phy/aquantia/Kconfig"

config AX88796B_PHY

diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile

index XXXXXXX..XXXXXXX 100644

--- a/drivers/net/phy/Makefile

+++ b/drivers/net/phy/Makefile

@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o

obj-$(CONFIG_AMD_PHY)        += amd.o

obj-$(CONFIG_AMCC_QT2025_PHY)    += qt2025.o

obj-$(CONFIG_AQUANTIA_PHY)    += aquantia/

+obj-$(CONFIG_AS21XXX_PHY)    += as21xxx.o

ifdef CONFIG_AX88796B_RUST_PHY

obj-$(CONFIG_AX88796B_PHY)    += ax88796b_rust.o

else

diff --git a/drivers/net/phy/as21xxx.c b/drivers/net/phy/as21xxx.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/drivers/net/phy/as21xxx.c

@@ -XXX,XX +XXX,XX @@

+// SPDX-License-Identifier: GPL-2.0

+/*

+ * Aeonsemi AS21XXxX PHY Driver

+ *

+ * Author: Christian Marangi <ansuelsmth@gmail.com>

+ */

+

+#include <linux/bitfield.h>

+#include <linux/firmware.h>

+#include <linux/module.h>

+#include <linux/of.h>

+#include <linux/phy.h>

+

+#define VEND1_GLB_REG_CPU_RESET_ADDR_LO_BASEADDR 0x3

+#define VEND1_GLB_REG_CPU_RESET_ADDR_HI_BASEADDR 0x4

+

+#define VEND1_GLB_REG_CPU_CTRL        0xe

+#define VEND1_GLB_CPU_CTRL_MASK    GENMASK(4, 0)

+#define VEND1_GLB_CPU_CTRL_LED_POLARITY_MASK GENMASK(12, 8)

+#define VEND1_GLB_CPU_CTRL_LED_POLARITY(_n) FIELD_PREP(VEND1_GLB_CPU_CTRL_LED_POLARITY_MASK, \

+                             BIT(_n))

+

+#define VEND1_FW_START_ADDR        0x100

+

+#define VEND1_GLB_REG_MDIO_INDIRECT_ADDRCMD 0x101

+#define VEND1_GLB_REG_MDIO_INDIRECT_LOAD 0x102

+

+#define VEND1_GLB_REG_MDIO_INDIRECT_STATUS 0x103

+

+#define VEND1_PTP_CLK            0x142

+#define VEND1_PTP_CLK_EN        BIT(6)

+

+/* 5 LED at step of 0x20

+ * FE: Fast-Ethernet (10/100)

+ * GE: Gigabit-Ethernet (1000)

+ * NG: New-Generation (2500/5000/10000)

+ */

+#define VEND1_LED_REG(_n)        (0x1800 + ((_n) * 0x10))

+#define VEND1_LED_REG_A_EVENT        GENMASK(15, 11)

+#define VEND1_LED_CONF            0x1881

+#define VEND1_LED_CONFG_BLINK        GENMASK(7, 0)

+

+#define VEND1_SPEED_STATUS        0x4002

+#define VEND1_SPEED_MASK        GENMASK(7, 0)

+#define VEND1_SPEED_10000        FIELD_PREP_CONST(VEND1_SPEED_MASK, 0x3)

+#define VEND1_SPEED_5000        FIELD_PREP_CONST(VEND1_SPEED_MASK, 0x5)

+#define VEND1_SPEED_2500        FIELD_PREP_CONST(VEND1_SPEED_MASK, 0x9)

+#define VEND1_SPEED_1000        FIELD_PREP_CONST(VEND1_SPEED_MASK, 0x10)

+#define VEND1_SPEED_100        FIELD_PREP_CONST(VEND1_SPEED_MASK, 0x20)

+#define VEND1_SPEED_10        FIELD_PREP_CONST(VEND1_SPEED_MASK, 0x0)

+

+#define VEND1_IPC_CMD            0x5801

+#define AEON_IPC_CMD_PARITY        BIT(15)

+#define AEON_IPC_CMD_SIZE        GENMASK(10, 6)

+#define AEON_IPC_CMD_OPCODE        GENMASK(5, 0)

+

+#define IPC_CMD_NOOP            0x0 /* Do nothing */

+#define IPC_CMD_INFO            0x1 /* Get Firmware Version */

+#define IPC_CMD_SYS_CPU            0x2 /* SYS_CPU */

+#define IPC_CMD_BULK_DATA        0xa /* Pass bulk data in ipc registers. */

+#define IPC_CMD_BULK_WRITE        0xc /* Write bulk data to memory */

+#define IPC_CMD_CFG_PARAM        0x1a /* Write config parameters to memory */

+#define IPC_CMD_NG_TESTMODE        0x1b /* Set NG test mode and tone */

+#define IPC_CMD_TEMP_MON        0x15 /* Temperature monitoring function */

+#define IPC_CMD_SET_LED            0x23 /* Set led */

+

+#define VEND1_IPC_STS            0x5802

+#define AEON_IPC_STS_PARITY        BIT(15)

+#define AEON_IPC_STS_SIZE        GENMASK(14, 10)

+#define AEON_IPC_STS_OPCODE        GENMASK(9, 4)

+#define AEON_IPC_STS_STATUS        GENMASK(3, 0)

+#define AEON_IPC_STS_STATUS_RCVD    FIELD_PREP_CONST(AEON_IPC_STS_STATUS, 0x1)

+#define AEON_IPC_STS_STATUS_PROCESS    FIELD_PREP_CONST(AEON_IPC_STS_STATUS, 0x2)

+#define AEON_IPC_STS_STATUS_SUCCESS    FIELD_PREP_CONST(AEON_IPC_STS_STATUS, 0x4)

+#define AEON_IPC_STS_STATUS_ERROR    FIELD_PREP_CONST(AEON_IPC_STS_STATUS, 0x8)

+#define AEON_IPC_STS_STATUS_BUSY    FIELD_PREP_CONST(AEON_IPC_STS_STATUS, 0xe)

+#define AEON_IPC_STS_STATUS_READY    FIELD_PREP_CONST(AEON_IPC_STS_STATUS, 0xf)

+

+#define VEND1_IPC_DATA0            0x5808

+#define VEND1_IPC_DATA1            0x5809

+#define VEND1_IPC_DATA2            0x580a

+#define VEND1_IPC_DATA3            0x580b

+#define VEND1_IPC_DATA4            0x580c

+#define VEND1_IPC_DATA5            0x580d

+#define VEND1_IPC_DATA6            0x580e

+#define VEND1_IPC_DATA7            0x580f

+#define VEND1_IPC_DATA(_n)        (VEND1_IPC_DATA0 + (_n))

+

+/* Sub command of CMD_INFO */

+#define IPC_INFO_VERSION        0x1

+

+/* Sub command of CMD_SYS_CPU */

+#define IPC_SYS_CPU_REBOOT        0x3

+#define IPC_SYS_CPU_IMAGE_OFST        0x4

+#define IPC_SYS_CPU_IMAGE_CHECK        0x5

+#define IPC_SYS_CPU_PHY_ENABLE        0x6

+

+/* Sub command of CMD_CFG_PARAM */

+#define IPC_CFG_PARAM_DIRECT        0x4

+

+/* CFG DIRECT sub command */

+#define IPC_CFG_PARAM_DIRECT_NG_PHYCTRL    0x1

+#define IPC_CFG_PARAM_DIRECT_CU_AN    0x2

+#define IPC_CFG_PARAM_DIRECT_SDS_PCS    0x3

+#define IPC_CFG_PARAM_DIRECT_AUTO_EEE    0x4

+#define IPC_CFG_PARAM_DIRECT_SDS_PMA    0x5

+#define IPC_CFG_PARAM_DIRECT_DPC_RA    0x6

+#define IPC_CFG_PARAM_DIRECT_DPC_PKT_CHK 0x7

+#define IPC_CFG_PARAM_DIRECT_DPC_SDS_WAIT_ETH 0x8

+#define IPC_CFG_PARAM_DIRECT_WDT    0x9

+#define IPC_CFG_PARAM_DIRECT_SDS_RESTART_AN 0x10

+#define IPC_CFG_PARAM_DIRECT_TEMP_MON    0x11

+#define IPC_CFG_PARAM_DIRECT_WOL    0x12

+

+/* Sub command of CMD_TEMP_MON */

+#define IPC_CMD_TEMP_MON_GET        0x4

+

+#define AS21XXX_MDIO_AN_C22        0xffe0

+

+#define PHY_ID_AS21XXX            0x75009410

+/* AS21xxx ID Legend

+ * AS21x1xxB1

+ * ^ ^^

+ * | |J: Supports SyncE/PTP

+ * | |P: No SyncE/PTP support

+ * | 1: Supports 2nd Serdes

+ * | 2: Not 2nd Serdes support

+ * 0: 10G, 5G, 2.5G

+ * 5: 5G, 2.5G

+ * 2: 2.5G

+ */

+#define PHY_ID_AS21011JB1        0x75009402

+#define PHY_ID_AS21011PB1        0x75009412

+#define PHY_ID_AS21010JB1        0x75009422

+#define PHY_ID_AS21010PB1        0x75009432

+#define PHY_ID_AS21511JB1        0x75009442

+#define PHY_ID_AS21511PB1        0x75009452

+#define PHY_ID_AS21510JB1        0x75009462

+#define PHY_ID_AS21510PB1        0x75009472

+#define PHY_ID_AS21210JB1        0x75009482

+#define PHY_ID_AS21210PB1        0x75009492

+#define PHY_VENDOR_AEONSEMI        0x75009400

+

+#define AEON_MAX_LDES            5

+#define AEON_IPC_DELAY            10000

+#define AEON_IPC_TIMEOUT        (AEON_IPC_DELAY * 100)

+#define AEON_IPC_DATA_MAX        (8 * sizeof(u16))

+

+#define AEON_BOOT_ADDR            0x1000

+#define AEON_CPU_BOOT_ADDR        0x2000

+#define AEON_CPU_CTRL_FW_LOAD        (BIT(4) | BIT(2) | BIT(1) | BIT(0))

+#define AEON_CPU_CTRL_FW_START        BIT(0)

+

+enum as21xxx_led_event {

+    VEND1_LED_REG_A_EVENT_ON_10 = 0x0,

+    VEND1_LED_REG_A_EVENT_ON_100,

+    VEND1_LED_REG_A_EVENT_ON_1000,

+    VEND1_LED_REG_A_EVENT_ON_2500,

+    VEND1_LED_REG_A_EVENT_ON_5000,

+    VEND1_LED_REG_A_EVENT_ON_10000,

+    VEND1_LED_REG_A_EVENT_ON_FE_GE,

+    VEND1_LED_REG_A_EVENT_ON_NG,

+    VEND1_LED_REG_A_EVENT_ON_FULL_DUPLEX,

+    VEND1_LED_REG_A_EVENT_ON_COLLISION,

+    VEND1_LED_REG_A_EVENT_BLINK_TX,

+    VEND1_LED_REG_A_EVENT_BLINK_RX,

+    VEND1_LED_REG_A_EVENT_BLINK_ACT,

+    VEND1_LED_REG_A_EVENT_ON_LINK,

+    VEND1_LED_REG_A_EVENT_ON_LINK_BLINK_ACT,

+    VEND1_LED_REG_A_EVENT_ON_LINK_BLINK_RX,

+    VEND1_LED_REG_A_EVENT_ON_FE_GE_BLINK_ACT,

+    VEND1_LED_REG_A_EVENT_ON_NG_BLINK_ACT,

+    VEND1_LED_REG_A_EVENT_ON_NG_BLINK_FE_GE,

+    VEND1_LED_REG_A_EVENT_ON_FD_BLINK_COLLISION,

+    VEND1_LED_REG_A_EVENT_ON,

+    VEND1_LED_REG_A_EVENT_OFF,

+};

+

+struct as21xxx_led_pattern_info {

+    unsigned int pattern;

+    u16 val;

+};

+

+struct as21xxx_priv {

+    bool parity_status;

+    /* Protect concurrent IPC access */

+    struct mutex ipc_lock;

+};

+

+static struct as21xxx_led_pattern_info as21xxx_led_supported_pattern[] = {

+    {

+        .pattern = BIT(TRIGGER_NETDEV_LINK_10),

+        .val = VEND1_LED_REG_A_EVENT_ON_10

+    },

+    {

+        .pattern = BIT(TRIGGER_NETDEV_LINK_100),

+        .val = VEND1_LED_REG_A_EVENT_ON_100

+    },

+    {

+        .pattern = BIT(TRIGGER_NETDEV_LINK_1000),

+        .val = VEND1_LED_REG_A_EVENT_ON_1000

+    },

+    {

+        .pattern = BIT(TRIGGER_NETDEV_LINK_2500),

+        .val = VEND1_LED_REG_A_EVENT_ON_2500

+    },

+    {

+        .pattern = BIT(TRIGGER_NETDEV_LINK_5000),

+        .val = VEND1_LED_REG_A_EVENT_ON_5000

+    },

+    {

+        .pattern = BIT(TRIGGER_NETDEV_LINK_10000),

+        .val = VEND1_LED_REG_A_EVENT_ON_10000

+    },

+    {

+        .pattern = BIT(TRIGGER_NETDEV_LINK),

+        .val = VEND1_LED_REG_A_EVENT_ON_LINK

+    },

+    {

+        .pattern = BIT(TRIGGER_NETDEV_LINK_10) |

+             BIT(TRIGGER_NETDEV_LINK_100) |

+             BIT(TRIGGER_NETDEV_LINK_1000),

+        .val = VEND1_LED_REG_A_EVENT_ON_FE_GE

+    },

+    {

+        .pattern = BIT(TRIGGER_NETDEV_LINK_2500) |

+             BIT(TRIGGER_NETDEV_LINK_5000) |

+             BIT(TRIGGER_NETDEV_LINK_10000),

+        .val = VEND1_LED_REG_A_EVENT_ON_NG

+    },

+    {

+        .pattern = BIT(TRIGGER_NETDEV_FULL_DUPLEX),

+        .val = VEND1_LED_REG_A_EVENT_ON_FULL_DUPLEX

+    },

+    {

+        .pattern = BIT(TRIGGER_NETDEV_TX),

+        .val = VEND1_LED_REG_A_EVENT_BLINK_TX

+    },

+    {

+        .pattern = BIT(TRIGGER_NETDEV_RX),

+        .val = VEND1_LED_REG_A_EVENT_BLINK_RX

+    },

+    {

+        .pattern = BIT(TRIGGER_NETDEV_TX) |

+             BIT(TRIGGER_NETDEV_RX),

+        .val = VEND1_LED_REG_A_EVENT_BLINK_ACT

+    },

+    {

+        .pattern = BIT(TRIGGER_NETDEV_LINK_10) |

+             BIT(TRIGGER_NETDEV_LINK_100) |

+             BIT(TRIGGER_NETDEV_LINK_1000) |

+             BIT(TRIGGER_NETDEV_LINK_2500) |

+             BIT(TRIGGER_NETDEV_LINK_5000) |

+             BIT(TRIGGER_NETDEV_LINK_10000),

+        .val = VEND1_LED_REG_A_EVENT_ON_LINK

+    },

+    {

+        .pattern = BIT(TRIGGER_NETDEV_LINK_10) |

+             BIT(TRIGGER_NETDEV_LINK_100) |

+             BIT(TRIGGER_NETDEV_LINK_1000) |

+             BIT(TRIGGER_NETDEV_LINK_2500) |

+             BIT(TRIGGER_NETDEV_LINK_5000) |

+             BIT(TRIGGER_NETDEV_LINK_10000) |

+             BIT(TRIGGER_NETDEV_TX) |

+             BIT(TRIGGER_NETDEV_RX),

+        .val = VEND1_LED_REG_A_EVENT_ON_LINK_BLINK_ACT

+    },

+    {

+        .pattern = BIT(TRIGGER_NETDEV_LINK_10) |

+             BIT(TRIGGER_NETDEV_LINK_100) |

+             BIT(TRIGGER_NETDEV_LINK_1000) |

+             BIT(TRIGGER_NETDEV_LINK_2500) |

+             BIT(TRIGGER_NETDEV_LINK_5000) |

+             BIT(TRIGGER_NETDEV_LINK_10000) |

+             BIT(TRIGGER_NETDEV_RX),

+        .val = VEND1_LED_REG_A_EVENT_ON_LINK_BLINK_RX

+    },

+    {

+        .pattern = BIT(TRIGGER_NETDEV_LINK_10) |

+             BIT(TRIGGER_NETDEV_LINK_100) |

+             BIT(TRIGGER_NETDEV_LINK_1000) |

+             BIT(TRIGGER_NETDEV_TX) |

+             BIT(TRIGGER_NETDEV_RX),

+        .val = VEND1_LED_REG_A_EVENT_ON_FE_GE_BLINK_ACT

+    },

+    {

+        .pattern = BIT(TRIGGER_NETDEV_LINK_2500) |

+             BIT(TRIGGER_NETDEV_LINK_5000) |

+             BIT(TRIGGER_NETDEV_LINK_10000) |

+             BIT(TRIGGER_NETDEV_TX) |

+             BIT(TRIGGER_NETDEV_RX),

+        .val = VEND1_LED_REG_A_EVENT_ON_NG_BLINK_ACT

+    }

+};

+

+static int aeon_firmware_boot(struct phy_device *phydev, const u8 *data,

+             size_t size)

+{

+    int i, ret;

+    u16 val;

+

+    ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLB_REG_CPU_CTRL,

+             VEND1_GLB_CPU_CTRL_MASK, AEON_CPU_CTRL_FW_LOAD);

+    if (ret)

+        return ret;

+

+    ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_FW_START_ADDR,

+             AEON_BOOT_ADDR);

+    if (ret)

+        return ret;

+

+    ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1,

+             VEND1_GLB_REG_MDIO_INDIRECT_ADDRCMD,

+             0x3ffc, 0xc000);

+    if (ret)

+        return ret;

+

+    val = phy_read_mmd(phydev, MDIO_MMD_VEND1,

+             VEND1_GLB_REG_MDIO_INDIRECT_STATUS);

+    if (val > 1) {

+        phydev_err(phydev, "wrong origin mdio_indirect_status: %x\n", val);

+        return -EINVAL;

+    }

+

+    /* Firmware is always aligned to u16 */

+    for (i = 0; i < size; i += 2) {

+        val = data[i + 1] << 8 | data[i];

+

+        ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,

+                 VEND1_GLB_REG_MDIO_INDIRECT_LOAD, val);

+        if (ret)

+            return ret;

+    }

+

+    ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,

+             VEND1_GLB_REG_CPU_RESET_ADDR_LO_BASEADDR,

+             lower_16_bits(AEON_CPU_BOOT_ADDR));

+    if (ret)

+        return ret;

+

+    ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,

+             VEND1_GLB_REG_CPU_RESET_ADDR_HI_BASEADDR,

+             upper_16_bits(AEON_CPU_BOOT_ADDR));

+    if (ret)

+        return ret;

+

+    return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLB_REG_CPU_CTRL,

+             VEND1_GLB_CPU_CTRL_MASK, AEON_CPU_CTRL_FW_START);

+}

+

+static int aeon_firmware_load(struct phy_device *phydev)

+{

+    struct device *dev = &phydev->mdio.dev;

+    const struct firmware *fw;

+    const char *fw_name;

+    int ret;

+

+    ret = of_property_read_string(dev->of_node, "firmware-name",

+                 &fw_name);

+    if (ret)

+        return ret;

+

+    ret = request_firmware(&fw, fw_name, dev);

+    if (ret) {

+        phydev_err(phydev, "failed to find FW file %s (%d)\n",

+             fw_name, ret);

+        return ret;

+    }

+

+    ret = aeon_firmware_boot(phydev, fw->data, fw->size);

+

+    release_firmware(fw);

+

+    return ret;

+}

+

+static int aeon_ipcs_wait_cmd(struct phy_device *phydev, bool parity_status)

+{

+    u16 val;

+

+    /* Exit condition logic:

+     * - Wait for parity bit equal

+     * - Wait for status success, error OR ready

+     */

+    return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, VEND1_IPC_STS, val,

+                     FIELD_GET(AEON_IPC_STS_PARITY, val) == parity_status &&

+                     (val & AEON_IPC_STS_STATUS) != AEON_IPC_STS_STATUS_RCVD &&

+                     (val & AEON_IPC_STS_STATUS) != AEON_IPC_STS_STATUS_PROCESS &&

+                     (val & AEON_IPC_STS_STATUS) != AEON_IPC_STS_STATUS_BUSY,

+                     AEON_IPC_DELAY, AEON_IPC_TIMEOUT, false);

+}

+

+static int aeon_ipc_send_cmd(struct phy_device *phydev,

+             struct as21xxx_priv *priv,

+             u16 cmd, u16 *ret_sts)

+{

+    bool curr_parity;

+    int ret;

+

+    /* The IPC sync by using a single parity bit.

+     * Each CMD have alternately this bit set or clear

+     * to understand correct flow and packet order.

+     */

+    curr_parity = priv->parity_status;

+    if (priv->parity_status)

+        cmd |= AEON_IPC_CMD_PARITY;

+

+    /* Always update parity for next packet */

+    priv->parity_status = !priv->parity_status;

+

+    ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_IPC_CMD, cmd);

+    if (ret)

+        return ret;

+

+    /* Wait for packet to be processed */

+    usleep_range(AEON_IPC_DELAY, AEON_IPC_DELAY + 5000);

+

+    /* With no ret_sts, ignore waiting for packet completion

+     * (ipc parity bit sync)

+     */

+    if (!ret_sts)

+        return 0;

+

+    ret = aeon_ipcs_wait_cmd(phydev, curr_parity);

+    if (ret)

+        return ret;

+

+    ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_IPC_STS);

+    if (ret < 0)

+        return ret;

+

+    *ret_sts = ret;

+    if ((*ret_sts & AEON_IPC_STS_STATUS) != AEON_IPC_STS_STATUS_SUCCESS)

+        return -EINVAL;

+

+    return 0;

+}

+

+static int aeon_ipc_send_msg(struct phy_device *phydev,

+             u16 opcode, u16 *data, unsigned int data_len,

+             u16 *ret_sts)

+{

+    struct as21xxx_priv *priv = phydev->priv;

+    u16 cmd;

+    int ret;

+    int i;

+

+    /* IPC have a max of 8 register to transfer data,

+     * make sure we never exceed this.

+     */

+    if (data_len > AEON_IPC_DATA_MAX)

+        return -EINVAL;

+

+    mutex_lock(&priv->ipc_lock);

+

+    for (i = 0; i < data_len / sizeof(u16); i++)

+        phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_IPC_DATA(i),

+             data[i]);

+

+    cmd = FIELD_PREP(AEON_IPC_CMD_SIZE, data_len) |

+     FIELD_PREP(AEON_IPC_CMD_OPCODE, opcode);

+    ret = aeon_ipc_send_cmd(phydev, priv, cmd, ret_sts);

+    if (ret)

+        phydev_err(phydev, "failed to send ipc msg for %x: %d\n",

+             opcode, ret);

+

+    mutex_unlock(&priv->ipc_lock);

+

+    return ret;

+}

+

+static int aeon_ipc_rcv_msg(struct phy_device *phydev,

+             u16 ret_sts, u16 *data)

+{

+    struct as21xxx_priv *priv = phydev->priv;

+    unsigned int size;

+    int ret;

+    int i;

+

+    if ((ret_sts & AEON_IPC_STS_STATUS) == AEON_IPC_STS_STATUS_ERROR)

+        return -EINVAL;

+

+    /* Prevent IPC from stack smashing the kernel */

+    size = FIELD_GET(AEON_IPC_STS_SIZE, ret_sts);

+    if (size > AEON_IPC_DATA_MAX)

+        return -EINVAL;

+

+    mutex_lock(&priv->ipc_lock);

+

+    for (i = 0; i < DIV_ROUND_UP(size, sizeof(u16)); i++) {

+        ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_IPC_DATA(i));

+        if (ret < 0) {

+            size = ret;

+            goto out;

+        }

+

+        data[i] = ret;

+    }

+

+out:

+    mutex_unlock(&priv->ipc_lock);

+

+    return size;

+}

+

+static int aeon_ipc_noop(struct phy_device *phydev,

+             struct as21xxx_priv *priv, u16 *ret_sts)

+{

+    u16 cmd;

+

+    cmd = FIELD_PREP(AEON_IPC_CMD_SIZE, 0) |

+     FIELD_PREP(AEON_IPC_CMD_OPCODE, IPC_CMD_NOOP);

+

+    return aeon_ipc_send_cmd(phydev, priv, cmd, ret_sts);

+}

+

+/* Logic to sync parity bit with IPC.

+ * We send 2 NOP cmd with same partity and we wait for IPC

+ * to handle the packet only for the second one. This way

+ * we make sure we are sync for every next cmd.

+ */

+static int aeon_ipc_sync_parity(struct phy_device *phydev,

+                struct as21xxx_priv *priv)

+{

+    u16 ret_sts;

+    int ret;

+

+    mutex_lock(&priv->ipc_lock);

+

+    /* Send NOP with no parity */

+    aeon_ipc_noop(phydev, priv, NULL);

+

+    /* Reset packet parity */

+    priv->parity_status = false;

+

+    /* Send second NOP with no parity */

+    ret = aeon_ipc_noop(phydev, priv, &ret_sts);

+

+    mutex_unlock(&priv->ipc_lock);

+

+    /* We expect to return -EINVAL */

+    if (ret != -EINVAL)

+        return ret;

+

+    if ((ret_sts & AEON_IPC_STS_STATUS) != AEON_IPC_STS_STATUS_READY) {

+        phydev_err(phydev, "Invalid IPC status on sync parity: %x\n",

+             ret_sts);

+        return -EINVAL;

+    }

+

+    return 0;

+}

+

+static int aeon_ipc_get_fw_version(struct phy_device *phydev)

+{

+    u16 ret_data[8], data[1];

+    u16 ret_sts;

+    int ret;

+

+    data[0] = IPC_INFO_VERSION;

+    ret = aeon_ipc_send_msg(phydev, IPC_CMD_INFO, data,

+                sizeof(data), &ret_sts);

+    if (ret)

+        return ret;

+

+    ret = aeon_ipc_rcv_msg(phydev, ret_sts, ret_data);

+    if (ret < 0)

+        return ret;

+

+    phydev_info(phydev, "Firmware Version: %s\n", (char *)ret_data);

+

+    return 0;

+}

+

+static int aeon_dpc_ra_enable(struct phy_device *phydev)

+{

+    u16 data[2];

+    u16 ret_sts;

+

+    data[0] = IPC_CFG_PARAM_DIRECT;

+    data[1] = IPC_CFG_PARAM_DIRECT_DPC_RA;

+

+    return aeon_ipc_send_msg(phydev, IPC_CMD_CFG_PARAM, data,

+                 sizeof(data), &ret_sts);

+}

+

+static int as21xxx_probe(struct phy_device *phydev)

+{

+    struct as21xxx_priv *priv;

+    int ret;

+

+    priv = devm_kzalloc(&phydev->mdio.dev,

+             sizeof(*priv), GFP_KERNEL);

+    if (!priv)

+        return -ENOMEM;

+    phydev->priv = priv;

+

+    ret = devm_mutex_init(&phydev->mdio.dev,

+             &priv->ipc_lock);

+    if (ret)

+        return ret;

+

+    ret = aeon_ipc_sync_parity(phydev, priv);

+    if (ret)

+        return ret;

+

+    ret = aeon_ipc_get_fw_version(phydev);

+    if (ret)

+        return ret;

+

+    /* Enable PTP clk if not already Enabled */

+    ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PTP_CLK,

+             VEND1_PTP_CLK_EN);

+    if (ret)

+        return ret;

+

+    return aeon_dpc_ra_enable(phydev);

+}

+

+static int as21xxx_read_link(struct phy_device *phydev, int *bmcr)

+{

+    int status;

+

+    /* Normal C22 BMCR report inconsistent data, use