Fix missing includes and struct declarations. Even if these don't cause

any compile issues at the moment, it's good to have them correct.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

---

drivers/gpu/drm/tidss/tidss_dispc.h | 3 +++

drivers/gpu/drm/tidss/tidss_drv.h | 2 ++

drivers/gpu/drm/tidss/tidss_plane.h | 2 ++

drivers/gpu/drm/tidss/tidss_scale_coefs.h | 2 ++

4 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h

index XXXXXXX..XXXXXXX 100644

--- a/drivers/gpu/drm/tidss/tidss_dispc.h

+++ b/drivers/gpu/drm/tidss/tidss_dispc.h

@@ -XXX,XX +XXX,XX @@

#ifndef __TIDSS_DISPC_H__

#define __TIDSS_DISPC_H__

+#include <drm/drm_color_mgmt.h>

+

#include "tidss_drv.h"

struct dispc_device;

struct drm_crtc_state;

+struct drm_plane_state;

enum tidss_gamma_type { TIDSS_GAMMA_8BIT, TIDSS_GAMMA_10BIT };

diff --git a/drivers/gpu/drm/tidss/tidss_drv.h b/drivers/gpu/drm/tidss/tidss_drv.h

index XXXXXXX..XXXXXXX 100644

--- a/drivers/gpu/drm/tidss/tidss_drv.h

+++ b/drivers/gpu/drm/tidss/tidss_drv.h

@@ -XXX,XX +XXX,XX @@

#include <linux/spinlock.h>

+#include <drm/drm_device.h>

+

#define TIDSS_MAX_PORTS 4

#define TIDSS_MAX_PLANES 4

diff --git a/drivers/gpu/drm/tidss/tidss_plane.h b/drivers/gpu/drm/tidss/tidss_plane.h

index XXXXXXX..XXXXXXX 100644

--- a/drivers/gpu/drm/tidss/tidss_plane.h

+++ b/drivers/gpu/drm/tidss/tidss_plane.h

@@ -XXX,XX +XXX,XX @@

#ifndef __TIDSS_PLANE_H__

#define __TIDSS_PLANE_H__

+#include <drm/drm_plane.h>

+

#define to_tidss_plane(p) container_of((p), struct tidss_plane, plane)

struct tidss_device;

diff --git a/drivers/gpu/drm/tidss/tidss_scale_coefs.h b/drivers/gpu/drm/tidss/tidss_scale_coefs.h

index XXXXXXX..XXXXXXX 100644

--- a/drivers/gpu/drm/tidss/tidss_scale_coefs.h

+++ b/drivers/gpu/drm/tidss/tidss_scale_coefs.h

@@ -XXX,XX +XXX,XX @@

#include <linux/types.h>

+struct device;

+

struct tidss_scale_coefs {

    s16 c2[16];

    s16 c1[16];

--

2.43.0

Use the crtc_* fields from drm_display_mode, instead of the "logical"

fields. This shouldn't change anything in practice, but afaiu the crtc_*

fields are the correct ones to use here.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

---

drivers/gpu/drm/tidss/tidss_crtc.c | 2 +-

drivers/gpu/drm/tidss/tidss_dispc.c | 16 ++++++++--------

2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/tidss/tidss_crtc.c b/drivers/gpu/drm/tidss/tidss_crtc.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/gpu/drm/tidss/tidss_crtc.c

+++ b/drivers/gpu/drm/tidss/tidss_crtc.c

@@ -XXX,XX +XXX,XX @@ static void tidss_crtc_atomic_enable(struct drm_crtc *crtc,

    tidss_runtime_get(tidss);

    r = dispc_vp_set_clk_rate(tidss->dispc, tcrtc->hw_videoport,

-                 mode->clock * 1000);

+                 mode->crtc_clock * 1000);

    if (r != 0)

        return;

diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/gpu/drm/tidss/tidss_dispc.c

+++ b/drivers/gpu/drm/tidss/tidss_dispc.c

@@ -XXX,XX +XXX,XX @@ void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,

    dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width);

-    hfp = mode->hsync_start - mode->hdisplay;

-    hsw = mode->hsync_end - mode->hsync_start;

-    hbp = mode->htotal - mode->hsync_end;

+    hfp = mode->crtc_hsync_start - mode->crtc_hdisplay;

+    hsw = mode->crtc_hsync_end - mode->crtc_hsync_start;

+    hbp = mode->crtc_htotal - mode->crtc_hsync_end;

-    vfp = mode->vsync_start - mode->vdisplay;

-    vsw = mode->vsync_end - mode->vsync_start;

-    vbp = mode->vtotal - mode->vsync_end;

+    vfp = mode->crtc_vsync_start - mode->crtc_vdisplay;

+    vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;

+    vbp = mode->crtc_vtotal - mode->crtc_vsync_end;

    dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H,

         FLD_VAL(hsw - 1, 7, 0) |

@@ -XXX,XX +XXX,XX @@ void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,

         FLD_VAL(ivs, 12, 12));

    dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN,

-         FLD_VAL(mode->hdisplay - 1, 11, 0) |

-         FLD_VAL(mode->vdisplay - 1, 27, 16));

+         FLD_VAL(mode->crtc_hdisplay - 1, 11, 0) |

+         FLD_VAL(mode->crtc_vdisplay - 1, 27, 16));

    VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0);

}

--

2.43.0

The DPHY driver does not return the actual hs_clk_rate, so the DSI

driver has no idea what clock was actually achieved. Set the realized

hs_clk_rate to the opts struct, so that the DSI driver gets it back.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

---

drivers/phy/cadence/cdns-dphy.c | 5 +++++

1 file changed, 5 insertions(+)

diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/phy/cadence/cdns-dphy.c

+++ b/drivers/phy/cadence/cdns-dphy.c

@@ -XXX,XX +XXX,XX @@ struct cdns_dphy_cfg {

    u8 pll_ipdiv;

    u8 pll_opdiv;

    u16 pll_fbdiv;

+    u32 hs_clk_rate;

    unsigned int nlanes;

};

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy,

                     cfg->pll_ipdiv,

                     pll_ref_hz);

+    cfg->hs_clk_rate = div_u64((u64)pll_ref_hz * cfg->pll_fbdiv,

+                 2 * cfg->pll_opdiv * cfg->pll_ipdiv);

+

    return 0;

}

@@ -XXX,XX +XXX,XX @@ static int cdns_dphy_config_from_opts(struct phy *phy,

    if (ret)

        return ret;

+    opts->hs_clk_rate = cfg->hs_clk_rate;

    opts->wakeup = cdns_dphy_get_wakeup_time_ns(dphy) / 1000;

    return 0;

--

2.43.0

The code in cdns-dphy has probably been part of a DSI driver in the

past. Remove DSI defines and variables which are not used or do not

actually do anything. Also rename cdns_dsi_get_dphy_pll_cfg() to

cdns_get_dphy_pll_cfg(), i.e. drop the "dsi", as it's not relevant here.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

---

drivers/phy/cadence/cdns-dphy.c | 19 ++++---------------

1 file changed, 4 insertions(+), 15 deletions(-)

diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/phy/cadence/cdns-dphy.c

+++ b/drivers/phy/cadence/cdns-dphy.c

@@ -XXX,XX +XXX,XX @@

#define DPHY_PSM_CFG_FROM_REG        BIT(0)

#define DPHY_PSM_CLK_DIV(x)        ((x) << 1)

-#define DSI_HBP_FRAME_OVERHEAD        12

-#define DSI_HSA_FRAME_OVERHEAD        14

-#define DSI_HFP_FRAME_OVERHEAD        6

-#define DSI_HSS_VSS_VSE_FRAME_OVERHEAD    4

-#define DSI_BLANKING_FRAME_OVERHEAD    6

-#define DSI_NULL_FRAME_OVERHEAD        6

-#define DSI_EOT_PKT_SIZE        4

-

#define DPHY_TX_J721E_WIZ_PLL_CTRL    0xF04

#define DPHY_TX_J721E_WIZ_STATUS    0xF08

#define DPHY_TX_J721E_WIZ_RST_CTRL    0xF0C

@@ -XXX,XX +XXX,XX @@ static const unsigned int tx_bands[] = {

    870, 950, 1000, 1200, 1400, 1600, 1800, 2000, 2200, 2500

};

-static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy,

-                 struct cdns_dphy_cfg *cfg,

-                 struct phy_configure_opts_mipi_dphy *opts,

-                 unsigned int *dsi_hfp_ext)

+static int cdns_get_dphy_pll_cfg(struct cdns_dphy *dphy,

+                 struct cdns_dphy_cfg *cfg,

+                 struct phy_configure_opts_mipi_dphy *opts)

{

    unsigned long pll_ref_hz = clk_get_rate(dphy->pll_ref_clk);

    u64 dlane_bps;

@@ -XXX,XX +XXX,XX @@ static int cdns_dphy_config_from_opts(struct phy *phy,

                 struct cdns_dphy_cfg *cfg)

{

    struct cdns_dphy *dphy = phy_get_drvdata(phy);

-    unsigned int dsi_hfp_ext = 0;

    int ret;

    ret = phy_mipi_dphy_config_validate(opts);

    if (ret)

        return ret;

-    ret = cdns_dsi_get_dphy_pll_cfg(dphy, cfg,

-                    opts, &dsi_hfp_ext);

+    ret = cdns_get_dphy_pll_cfg(dphy, cfg, opts);

    if (ret)

        return ret;

--

2.43.0

The Cadence DSI requires negative syncs from the incoming video signal,

but at the moment that requirement is not expressed in any way. If the

crtc decides to use positive syncs, things break down.

Use the adjusted_mode in atomic_check to set the sync flags to negative

ones.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

---

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 5 +++++

1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_bridge_atomic_check(struct drm_bridge *bridge,

    struct cdns_dsi_bridge_state *dsi_state = to_cdns_dsi_bridge_state(bridge_state);

    const struct drm_display_mode *mode = &crtc_state->mode;

    struct cdns_dsi_cfg *dsi_cfg = &dsi_state->dsi_cfg;

+    struct drm_display_mode *adjusted_crtc_mode = &crtc_state->adjusted_mode;

+

+    /* cdns-dsi requires negative syncs */

+    adjusted_crtc_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);

+    adjusted_crtc_mode->flags |= DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC;

    return cdns_dsi_check_conf(dsi, mode, dsi_cfg, false);

}

--

2.43.0

The phy_validate() can change the HS clock rate we passed to it in the

PHY config, depending on what the HW can actually do. The driver just

ignores this at the moment, but if the actual HS clock rate is different

than the requested one, the pipeline will fail as all the DSI timing

calculations will be incorrect.

There are ways to improve DSI operation for various clock rates, but for

now, just add a check to see if the rate changed, and return an error if

that happens.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

---

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 11 +++++++++++

1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_check_conf(struct cdns_dsi *dsi,

    unsigned long dsi_hss_hsa_hse_hbp;

    unsigned int nlanes = output->dev->lanes;

    int mode_clock = (mode_valid_check ? mode->clock : mode->crtc_clock);

+    unsigned long req_hs_clk_rate;

    int ret;

    ret = cdns_dsi_mode2cfg(dsi, mode, dsi_cfg, mode_valid_check);

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_check_conf(struct cdns_dsi *dsi,

    if (ret)

        return ret;

+    req_hs_clk_rate = output->phy_opts.mipi_dphy.hs_clk_rate;

    ret = phy_validate(dsi->dphy, PHY_MODE_MIPI_DPHY, 0, &output->phy_opts);

    if (ret)

        return ret;

+    if (req_hs_clk_rate != output->phy_opts.mipi_dphy.hs_clk_rate) {

+        dev_err(&dsi->dphy->dev,

+            "validation changed hs_clk_rate from %lu to %lu, diff %lu\n",

+            req_hs_clk_rate, output->phy_opts.mipi_dphy.hs_clk_rate,

+            output->phy_opts.mipi_dphy.hs_clk_rate -

+                req_hs_clk_rate);

+        return -EINVAL;

+    }

+

    dsi_hss_hsa_hse_hbp = dsi_cfg->hbp + DSI_HBP_FRAME_OVERHEAD;

    if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)

        dsi_hss_hsa_hse_hbp += dsi_cfg->hsa + DSI_HSA_FRAME_OVERHEAD;

--

2.43.0

Clean up the function a bit, mainly by doing the mode_valid_check dance

once in the beginning of the function, and grouping the calculations

wrt. sync/event mode a bit better.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

---

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 48 ++++++++++++--------------

1 file changed, 22 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi,

             bool mode_valid_check)

{

    struct cdns_dsi_output *output = &dsi->output;

-    unsigned int tmp;

-    bool sync_pulse = false;

+    u32 dpi_hsa, dpi_hbp, dpi_hfp, dpi_hact;

+    bool sync_pulse;

    int bpp;

+    if (mode_valid_check) {

+        dpi_hsa = mode->hsync_end - mode->hsync_start;

+        dpi_hbp = mode->htotal - mode->hsync_end;

+        dpi_hfp = mode->hsync_start - mode->hdisplay;

+        dpi_hact = mode->hdisplay;

+    } else {

+        dpi_hsa = mode->crtc_hsync_end - mode->crtc_hsync_start;

+        dpi_hbp = mode->crtc_htotal - mode->crtc_hsync_end;

+        dpi_hfp = mode->crtc_hsync_start - mode->crtc_hdisplay;

+        dpi_hact = mode->crtc_hdisplay;

+    }

+

    memset(dsi_cfg, 0, sizeof(*dsi_cfg));

-    if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)

-        sync_pulse = true;

+    sync_pulse = output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE;

    bpp = mipi_dsi_pixel_format_to_bpp(output->dev->format);

-    if (mode_valid_check)

-        tmp = mode->htotal -

-         (sync_pulse ? mode->hsync_end : mode->hsync_start);

-    else

-        tmp = mode->crtc_htotal -

-         (sync_pulse ?

-         mode->crtc_hsync_end : mode->crtc_hsync_start);

-

-    dsi_cfg->hbp = dpi_to_dsi_timing(tmp, bpp, DSI_HBP_FRAME_OVERHEAD);

+    dsi_cfg->hbp = dpi_to_dsi_timing(dpi_hbp + (sync_pulse ? 0 : dpi_hsa),

+                     bpp, DSI_HBP_FRAME_OVERHEAD);

-    if (sync_pulse) {

-        if (mode_valid_check)

-            tmp = mode->hsync_end - mode->hsync_start;

-        else

-            tmp = mode->crtc_hsync_end - mode->crtc_hsync_start;

+    if (sync_pulse)

+        dsi_cfg->hsa =

+            dpi_to_dsi_timing(dpi_hsa, bpp, DSI_HSA_FRAME_OVERHEAD);

-        dsi_cfg->hsa = dpi_to_dsi_timing(tmp, bpp,

-                         DSI_HSA_FRAME_OVERHEAD);

-    }

+    dsi_cfg->hact = dpi_to_dsi_timing(dpi_hact, bpp, 0);

-    dsi_cfg->hact = dpi_to_dsi_timing(mode_valid_check ?

-                     mode->hdisplay : mode->crtc_hdisplay,

-                     bpp, 0);

-    dsi_cfg->hfp = dpi_to_dsi_timing(mode_to_dpi_hfp(mode, mode_valid_check),

-                     bpp, DSI_HFP_FRAME_OVERHEAD);

+    dsi_cfg->hfp = dpi_to_dsi_timing(dpi_hfp, bpp, DSI_HFP_FRAME_OVERHEAD);

    return 0;

}

--

2.43.0

The driver tries to calculate the value for REG_WAKEUP_TIME. However,

the calculation itself is not correct, and to add on it, the resulting

value is almost always larger than the field's size, so the actual

result is more or less random.

According to the docs, figuring out the value for REG_WAKEUP_TIME

requires HW characterization and there's no way to have a generic

algorithm to come up with the value. That doesn't help at all...

However, we know that the value must be smaller than the line time, and,

at least in my understanding, the proper value for it is quite small.

Testing shows that setting it to 1/10 of the line time seems to work

well. All video modes from my HDMI monitor work with this algorithm.

Hopefully we'll get more information on how to calculate the value, and

we can then update this.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

---

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 8 +++++++-

1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

@@ -XXX,XX +XXX,XX @@ static void cdns_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge,

    tx_byte_period = DIV_ROUND_DOWN_ULL((u64)NSEC_PER_SEC * 8,

                     phy_cfg->hs_clk_rate);

-    reg_wakeup = (phy_cfg->hs_prepare + phy_cfg->hs_zero) / tx_byte_period;

+

+    /*

+     * Estimated time [in clock cycles] to perform LP->HS on D-PHY.

+     * It is not clear how to calculate this, so for now,

+     * set it to 1/10 of the total number of clocks in a line.

+     */

+    reg_wakeup = dsi_cfg.htotal / nlanes / 10;

    writel(REG_WAKEUP_TIME(reg_wakeup) | REG_LINE_DURATION(tmp),

     dsi->regs + VID_DPHY_TIME);

--

2.43.0

The timings calculation gets it wrong for DSI event mode, resulting in

too large hbp value. Fix the issue by taking into account the

pulse/event mode difference.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

---

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 33 ++++++++++++++++++--------

1 file changed, 23 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

@@ -XXX,XX +XXX,XX @@

#define DSI_OUTPUT_PORT            0

#define DSI_INPUT_PORT(inputid)        (1 + (inputid))

-#define DSI_HBP_FRAME_OVERHEAD        12

+#define DSI_HBP_FRAME_PULSE_OVERHEAD    12

+#define DSI_HBP_FRAME_EVENT_OVERHEAD    16

#define DSI_HSA_FRAME_OVERHEAD        14

#define DSI_HFP_FRAME_OVERHEAD        6

#define DSI_HSS_VSS_VSE_FRAME_OVERHEAD    4

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi,

    bpp = mipi_dsi_pixel_format_to_bpp(output->dev->format);

-    dsi_cfg->hbp = dpi_to_dsi_timing(dpi_hbp + (sync_pulse ? 0 : dpi_hsa),

-                     bpp, DSI_HBP_FRAME_OVERHEAD);

+    if (sync_pulse) {

+        dsi_cfg->hbp = dpi_to_dsi_timing(dpi_hbp, bpp,

+                         DSI_HBP_FRAME_PULSE_OVERHEAD);

-    if (sync_pulse)

-        dsi_cfg->hsa =

-            dpi_to_dsi_timing(dpi_hsa, bpp, DSI_HSA_FRAME_OVERHEAD);

+        dsi_cfg->hsa = dpi_to_dsi_timing(dpi_hsa, bpp,

+                         DSI_HSA_FRAME_OVERHEAD);

+    } else {

+        dsi_cfg->hbp = dpi_to_dsi_timing(dpi_hbp + dpi_hsa, bpp,

+                         DSI_HBP_FRAME_EVENT_OVERHEAD);

+

+        dsi_cfg->hsa = 0;

+    }

    dsi_cfg->hact = dpi_to_dsi_timing(dpi_hact, bpp, 0);

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_adjust_phy_config(struct cdns_dsi *dsi,

    unsigned int dsi_hfp_ext;

    unsigned int lanes = output->dev->lanes;

-    dsi_htotal = dsi_cfg->hbp + DSI_HBP_FRAME_OVERHEAD;

-    if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)

+    if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {

+        dsi_htotal = dsi_cfg->hbp + DSI_HBP_FRAME_PULSE_OVERHEAD;

        dsi_htotal += dsi_cfg->hsa + DSI_HSA_FRAME_OVERHEAD;

+    } else {

+        dsi_htotal = dsi_cfg->hbp + DSI_HBP_FRAME_EVENT_OVERHEAD;

+    }

    dsi_htotal += dsi_cfg->hact;

    dsi_htotal += dsi_cfg->hfp + DSI_HFP_FRAME_OVERHEAD;

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_check_conf(struct cdns_dsi *dsi,

        return -EINVAL;

    }

-    dsi_hss_hsa_hse_hbp = dsi_cfg->hbp + DSI_HBP_FRAME_OVERHEAD;

-    if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)

+    if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {

+        dsi_hss_hsa_hse_hbp = dsi_cfg->hbp + DSI_HBP_FRAME_PULSE_OVERHEAD;

        dsi_hss_hsa_hse_hbp += dsi_cfg->hsa + DSI_HSA_FRAME_OVERHEAD;

+    } else {

+        dsi_hss_hsa_hse_hbp = dsi_cfg->hbp + DSI_HBP_FRAME_EVENT_OVERHEAD;

+    }

    /*

     * Make sure DPI(HFP) > DSI(HSS+HSA+HSE+HBP) to guarantee that the FIFO

--

2.43.0

The driver check if "DPI(HFP) > DSI(HSS+HSA+HSE+HBP)", and rejects the

mode if not.

However, testing shows that this doesn't hold at all. I can set the hfp

to very small values, with no errors. The feedback from the HW team also

was that the check is not right, although it's not clear if there's a

way to validate the FIFO emptying.

The check rejects quite a lot of modes, apparently for no good reason,

so drop the check.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

---

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 28 --------------------------

1 file changed, 28 deletions(-)

diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

@@ -XXX,XX +XXX,XX @@ bridge_to_cdns_dsi_input(struct drm_bridge *bridge)

    return container_of(bridge, struct cdns_dsi_input, bridge);

}

-static unsigned int mode_to_dpi_hfp(const struct drm_display_mode *mode,

-                 bool mode_valid_check)

-{

-    if (mode_valid_check)

-        return mode->hsync_start - mode->hdisplay;

-

-    return mode->crtc_hsync_start - mode->crtc_hdisplay;

-}

-

static unsigned int dpi_to_dsi_timing(unsigned int dpi_timing,

                 unsigned int dpi_bpp,

                 unsigned int dsi_pkt_overhead)

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_check_conf(struct cdns_dsi *dsi,

{

    struct cdns_dsi_output *output = &dsi->output;

    struct phy_configure_opts_mipi_dphy *phy_cfg = &output->phy_opts.mipi_dphy;

-    unsigned long dsi_hss_hsa_hse_hbp;

    unsigned int nlanes = output->dev->lanes;

    int mode_clock = (mode_valid_check ? mode->clock : mode->crtc_clock);

    unsigned long req_hs_clk_rate;

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_check_conf(struct cdns_dsi *dsi,

        return -EINVAL;

    }

-    if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {

-        dsi_hss_hsa_hse_hbp = dsi_cfg->hbp + DSI_HBP_FRAME_PULSE_OVERHEAD;

-        dsi_hss_hsa_hse_hbp += dsi_cfg->hsa + DSI_HSA_FRAME_OVERHEAD;

-    } else {

-        dsi_hss_hsa_hse_hbp = dsi_cfg->hbp + DSI_HBP_FRAME_EVENT_OVERHEAD;

-    }

-

-    /*

-     * Make sure DPI(HFP) > DSI(HSS+HSA+HSE+HBP) to guarantee that the FIFO

-     * is empty before we start a receiving a new line on the DPI

-     * interface.

-     */

-    if ((u64)phy_cfg->hs_clk_rate *

-     mode_to_dpi_hfp(mode, mode_valid_check) * nlanes <

-     (u64)dsi_hss_hsa_hse_hbp *

-     (mode_valid_check ? mode->clock : mode->crtc_clock) * 1000)

-        return -EINVAL;

-

    return 0;

}

--

2.43.0

The docs say about mode_valid():

"it is not allowed to look at anything else but the passed-in mode, and

validate it against configuration-invariant hardware constraints"

We're doing a lot more than just looking at the mode. The main issue

here is that we're doing checks based on the pixel clock, before we know

what the pixel clock from the crtc actually is.

So, drop the checks from .mode_valid(). This also allows us to remove

the 'mode_valid_check' parameter from internal functions, and the

related code.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

---

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 44 ++++++++------------------

1 file changed, 14 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

@@ -XXX,XX +XXX,XX @@ static unsigned int dpi_to_dsi_timing(unsigned int dpi_timing,

static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi,

             const struct drm_display_mode *mode,

-             struct cdns_dsi_cfg *dsi_cfg,

-             bool mode_valid_check)

+             struct cdns_dsi_cfg *dsi_cfg)

{

    struct cdns_dsi_output *output = &dsi->output;

    u32 dpi_hsa, dpi_hbp, dpi_hfp, dpi_hact;

    bool sync_pulse;

    int bpp;

-    if (mode_valid_check) {

-        dpi_hsa = mode->hsync_end - mode->hsync_start;

-        dpi_hbp = mode->htotal - mode->hsync_end;

-        dpi_hfp = mode->hsync_start - mode->hdisplay;

-        dpi_hact = mode->hdisplay;

-    } else {

-        dpi_hsa = mode->crtc_hsync_end - mode->crtc_hsync_start;

-        dpi_hbp = mode->crtc_htotal - mode->crtc_hsync_end;

-        dpi_hfp = mode->crtc_hsync_start - mode->crtc_hdisplay;

-        dpi_hact = mode->crtc_hdisplay;

-    }

+    dpi_hsa = mode->crtc_hsync_end - mode->crtc_hsync_start;

+    dpi_hbp = mode->crtc_htotal - mode->crtc_hsync_end;

+    dpi_hfp = mode->crtc_hsync_start - mode->crtc_hdisplay;

+    dpi_hact = mode->crtc_hdisplay;

    memset(dsi_cfg, 0, sizeof(*dsi_cfg));

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi,

static int cdns_dsi_adjust_phy_config(struct cdns_dsi *dsi,

             struct cdns_dsi_cfg *dsi_cfg,

             struct phy_configure_opts_mipi_dphy *phy_cfg,

-             const struct drm_display_mode *mode,

-             bool mode_valid_check)

+             const struct drm_display_mode *mode)

{

    struct cdns_dsi_output *output = &dsi->output;

    unsigned long long dlane_bps;

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_adjust_phy_config(struct cdns_dsi *dsi,

    if (dsi_htotal % lanes)

        adj_dsi_htotal += lanes - (dsi_htotal % lanes);

-    dpi_hz = (mode_valid_check ? mode->clock : mode->crtc_clock) * 1000;

+    dpi_hz = mode->crtc_clock * 1000;

    dlane_bps = (unsigned long long)dpi_hz * adj_dsi_htotal;

    /* data rate in bytes/sec is not an integer, refuse the mode. */

-    dpi_htotal = mode_valid_check ? mode->htotal : mode->crtc_htotal;

+    dpi_htotal = mode->crtc_htotal;

    if (do_div(dlane_bps, lanes * dpi_htotal))

        return -EINVAL;

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_adjust_phy_config(struct cdns_dsi *dsi,

static int cdns_dsi_check_conf(struct cdns_dsi *dsi,

             const struct drm_display_mode *mode,

-             struct cdns_dsi_cfg *dsi_cfg,

-             bool mode_valid_check)

+             struct cdns_dsi_cfg *dsi_cfg)

{

    struct cdns_dsi_output *output = &dsi->output;

    struct phy_configure_opts_mipi_dphy *phy_cfg = &output->phy_opts.mipi_dphy;

    unsigned int nlanes = output->dev->lanes;

-    int mode_clock = (mode_valid_check ? mode->clock : mode->crtc_clock);

    unsigned long req_hs_clk_rate;

    int ret;

-    ret = cdns_dsi_mode2cfg(dsi, mode, dsi_cfg, mode_valid_check);

+    ret = cdns_dsi_mode2cfg(dsi, mode, dsi_cfg);

    if (ret)

        return ret;

-    ret = phy_mipi_dphy_get_default_config(mode_clock * 1000,

+    ret = phy_mipi_dphy_get_default_config(mode->crtc_clock * 1000,

                     mipi_dsi_pixel_format_to_bpp(output->dev->format),

                     nlanes, phy_cfg);

    if (ret)

        return ret;

-    ret = cdns_dsi_adjust_phy_config(dsi, dsi_cfg, phy_cfg, mode, mode_valid_check);

+    ret = cdns_dsi_adjust_phy_config(dsi, dsi_cfg, phy_cfg, mode);

    if (ret)

        return ret;

@@ -XXX,XX +XXX,XX @@ cdns_dsi_bridge_mode_valid(struct drm_bridge *bridge,

    struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);

    struct cdns_dsi *dsi = input_to_dsi(input);

    struct cdns_dsi_output *output = &dsi->output;

-    struct cdns_dsi_cfg dsi_cfg;

-    int bpp, ret;

+    int bpp;

    /*

     * VFP_DSI should be less than VFP_DPI and VFP_DSI should be at

@@ -XXX,XX +XXX,XX @@ cdns_dsi_bridge_mode_valid(struct drm_bridge *bridge,

    if ((mode->hdisplay * bpp) % 32)

        return MODE_H_ILLEGAL;

-    ret = cdns_dsi_check_conf(dsi, mode, &dsi_cfg, true);

-    if (ret)

-        return MODE_BAD;

-

    return MODE_OK;

}

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_bridge_atomic_check(struct drm_bridge *bridge,

    adjusted_crtc_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);

    adjusted_crtc_mode->flags |= DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC;

-    return cdns_dsi_check_conf(dsi, mode, dsi_cfg, false);

+    return cdns_dsi_check_conf(dsi, mode, dsi_cfg);

}

static struct drm_bridge_state *

--

2.43.0

The driver uses crtc_* fields from the mode. While I think in the

enable-path this would be correct, I do not think it's correct in the

check phase, as the crtc hasn't had a chance to update the crtc_* fields

yet.

Overall, my understanding is that the crtc_* fields are relevant only in

cases where we have things like interlace or double pixel mode, where we

have a logical and real timings. We never use those with DSI, so the

crtc_* fields should just always match the normal values.

So, drop the use of crtc_* values.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

---

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 22 +++++++++++-----------

1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi,

    bool sync_pulse;

    int bpp;

-    dpi_hsa = mode->crtc_hsync_end - mode->crtc_hsync_start;

-    dpi_hbp = mode->crtc_htotal - mode->crtc_hsync_end;

-    dpi_hfp = mode->crtc_hsync_start - mode->crtc_hdisplay;

-    dpi_hact = mode->crtc_hdisplay;

+    dpi_hsa = mode->hsync_end - mode->hsync_start;

+    dpi_hbp = mode->htotal - mode->hsync_end;

+    dpi_hfp = mode->hsync_start - mode->hdisplay;

+    dpi_hact = mode->hdisplay;

    memset(dsi_cfg, 0, sizeof(*dsi_cfg));

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_adjust_phy_config(struct cdns_dsi *dsi,

    if (dsi_htotal % lanes)

        adj_dsi_htotal += lanes - (dsi_htotal % lanes);

-    dpi_hz = mode->crtc_clock * 1000;

+    dpi_hz = mode->clock * 1000;

    dlane_bps = (unsigned long long)dpi_hz * adj_dsi_htotal;

    /* data rate in bytes/sec is not an integer, refuse the mode. */

-    dpi_htotal = mode->crtc_htotal;

+    dpi_htotal = mode->htotal;

    if (do_div(dlane_bps, lanes * dpi_htotal))

        return -EINVAL;

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_check_conf(struct cdns_dsi *dsi,

    if (ret)

        return ret;

-    ret = phy_mipi_dphy_get_default_config(mode->crtc_clock * 1000,

+    ret = phy_mipi_dphy_get_default_config(mode->clock * 1000,

                     mipi_dsi_pixel_format_to_bpp(output->dev->format),

                     nlanes, phy_cfg);

    if (ret)

@@ -XXX,XX +XXX,XX @@ static void cdns_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge,

    writel(HFP_LEN(dsi_cfg.hfp) | HACT_LEN(dsi_cfg.hact),

     dsi->regs + VID_HSIZE2);

-    writel(VBP_LEN(mode->crtc_vtotal - mode->crtc_vsync_end - 1) |

-     VFP_LEN(mode->crtc_vsync_start - mode->crtc_vdisplay) |

-     VSA_LEN(mode->crtc_vsync_end - mode->crtc_vsync_start + 1),

+    writel(VBP_LEN(mode->vtotal - mode->vsync_end - 1) |

+     VFP_LEN(mode->vsync_start - mode->vdisplay) |

+     VSA_LEN(mode->vsync_end - mode->vsync_start + 1),

     dsi->regs + VID_VSIZE1);

-    writel(mode->crtc_vdisplay, dsi->regs + VID_VSIZE2);

+    writel(mode->vdisplay, dsi->regs + VID_VSIZE2);

    tmp = dsi_cfg.htotal -

     (dsi_cfg.hsa + DSI_BLANKING_FRAME_OVERHEAD +

--

2.43.0

The drm_display_mode is a bit difficult one to use (we need hfp, hbp,

... instead of hsync_start, hsync_end, ...) and understand (when to use

crtc_* fields).

To simplify the code, use struct videomode internally which cleans up

the code. If in the future we want to use crtc_* fields in some code

patchs, that can be easily achieved by creating a videomode from the

crtc_* fields, and no change to the functions that do the work is

needed.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

---

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 31 +++++++++++++++-----------

1 file changed, 18 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

@@ -XXX,XX +XXX,XX @@

#include <drm/drm_drv.h>

#include <drm/drm_probe_helper.h>

#include <video/mipi_display.h>

+#include <video/videomode.h>

#include <linux/clk.h>

#include <linux/interrupt.h>

@@ -XXX,XX +XXX,XX @@ static unsigned int dpi_to_dsi_timing(unsigned int dpi_timing,

}

static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi,

-             const struct drm_display_mode *mode,

+             const struct videomode *vm,

             struct cdns_dsi_cfg *dsi_cfg)

{

    struct cdns_dsi_output *output = &dsi->output;

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi,

    bool sync_pulse;

    int bpp;

-    dpi_hsa = mode->hsync_end - mode->hsync_start;

-    dpi_hbp = mode->htotal - mode->hsync_end;

-    dpi_hfp = mode->hsync_start - mode->hdisplay;

-    dpi_hact = mode->hdisplay;

+    dpi_hsa = vm->hsync_len;

+    dpi_hbp = vm->hback_porch;

+    dpi_hfp = vm->hfront_porch;

+    dpi_hact = vm->hactive;

    memset(dsi_cfg, 0, sizeof(*dsi_cfg));

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi,

static int cdns_dsi_adjust_phy_config(struct cdns_dsi *dsi,

             struct cdns_dsi_cfg *dsi_cfg,

             struct phy_configure_opts_mipi_dphy *phy_cfg,

-             const struct drm_display_mode *mode)

+             const struct videomode *vm)

{

    struct cdns_dsi_output *output = &dsi->output;

    unsigned long long dlane_bps;

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_adjust_phy_config(struct cdns_dsi *dsi,

    if (dsi_htotal % lanes)

        adj_dsi_htotal += lanes - (dsi_htotal % lanes);

-    dpi_hz = mode->clock * 1000;

+    dpi_hz = vm->pixelclock;

    dlane_bps = (unsigned long long)dpi_hz * adj_dsi_htotal;

    /* data rate in bytes/sec is not an integer, refuse the mode. */

-    dpi_htotal = mode->htotal;

+    dpi_htotal = vm->hactive + vm->hfront_porch + vm->hback_porch +

+         vm->hsync_len;

    if (do_div(dlane_bps, lanes * dpi_htotal))

        return -EINVAL;

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_adjust_phy_config(struct cdns_dsi *dsi,

}

static int cdns_dsi_check_conf(struct cdns_dsi *dsi,

-             const struct drm_display_mode *mode,

+             const struct videomode *vm,

             struct cdns_dsi_cfg *dsi_cfg)

{

    struct cdns_dsi_output *output = &dsi->output;

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_check_conf(struct cdns_dsi *dsi,

    unsigned long req_hs_clk_rate;

    int ret;

-    ret = cdns_dsi_mode2cfg(dsi, mode, dsi_cfg);

+    ret = cdns_dsi_mode2cfg(dsi, vm, dsi_cfg);

    if (ret)

        return ret;

-    ret = phy_mipi_dphy_get_default_config(mode->clock * 1000,

+    ret = phy_mipi_dphy_get_default_config(vm->pixelclock,

                     mipi_dsi_pixel_format_to_bpp(output->dev->format),

                     nlanes, phy_cfg);

    if (ret)

        return ret;

-    ret = cdns_dsi_adjust_phy_config(dsi, dsi_cfg, phy_cfg, mode);

+    ret = cdns_dsi_adjust_phy_config(dsi, dsi_cfg, phy_cfg, vm);

    if (ret)

        return ret;

@@ -XXX,XX +XXX,XX @@ static int cdns_dsi_bridge_atomic_check(struct drm_bridge *bridge,

    const struct drm_display_mode *mode = &crtc_state->mode;

    struct cdns_dsi_cfg *dsi_cfg = &dsi_state->dsi_cfg;

    struct drm_display_mode *adjusted_crtc_mode = &crtc_state->adjusted_mode;

+    struct videomode vm;

    /* cdns-dsi requires negative syncs */

    adjusted_crtc_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);

    adjusted_crtc_mode->flags |= DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC;

-    return cdns_dsi_check_conf(dsi, mode, dsi_cfg);

+    drm_display_mode_to_videomode(mode, &vm);

+

+    return cdns_dsi_check_conf(dsi, &vm, dsi_cfg);

}

static struct drm_bridge_state *

--

2.43.0

The driver currently expects the pixel clock and the HS clock to be

compatible, but the DPHY PLL doesn't give very finely grained rates.

This often leads to the situation where the pipeline just fails, as the

resulting HS clock is just too off.

We could change the driver to do a better job on adjusting the DSI

blanking values, hopefully getting a working pipeline even if the pclk

and HS clocks are not exactly compatible. But that is a bigger work.

What we can do easily is to see in .atomic_check() what HS clock rate we

can get, based on the pixel clock rate, and then convert the HS clock

rate back to pixel clock rate and ask that rate from the crtc. If the

crtc has a good PLL (which is the case for TI K3 SoCs), this will fix

any issues wrt. the clock rates.

If the crtc cannot provide the requested clock, well, we're no worse off

with this patch than what we have at the moment.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

---

drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 39 +++++++++++++++++++++++++-

1 file changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

index XXXXXXX..XXXXXXX 100644

--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c

@@ -XXX,XX +XXX,XX @@ static u32 *cdns_dsi_bridge_get_input_bus_fmts(struct drm_bridge *bridge,

    return input_fmts;

}

+static long cdns_dsi_round_pclk(struct cdns_dsi *dsi, unsigned long pclk)

+{

+    struct cdns_dsi_output *output = &dsi->output;

+    unsigned int nlanes = output->dev->lanes;

+    union phy_configure_opts phy_opts = { 0 };

+    u32 bitspp;

+    int ret;

+

+    bitspp = mipi_dsi_pixel_format_to_bpp(output->dev->format);

+

+    ret = phy_mipi_dphy_get_default_config(pclk, bitspp, nlanes,

+                     &phy_opts.mipi_dphy);

+    if (ret)

+        return ret;

+

+    ret = phy_validate(dsi->dphy, PHY_MODE_MIPI_DPHY, 0, &phy_opts);

+    if (ret)

+        return ret;

+

+    return div64_u64((u64)phy_opts.mipi_dphy.hs_clk_rate * nlanes, bitspp);

+}

+

static int cdns_dsi_bridge_atomic_check(struct drm_bridge *bridge,

                    struct drm_bridge_state *bridge_state,

                    struct drm_crtc_state *crtc_state,