...
...
4
K3 SoCs all match what is already done for J784s4.
4
K3 SoCs all match what is already done for J784s4.
5
5
6
No functional change, DT changes are fully backwards and forwards
6
No functional change, DT changes are fully backwards and forwards
7
compatible.
7
compatible.
8
8
9
Thanks,
9
[0]: commit cc1965b02d6c ("dt-bindings: mfd: syscon: Add ti,j784s4-pcie-ctrl compatible")
10
Andrew
10
<https://lore.kernel.org/all/20240204090336.3209063-1-s-vadapalli@ti.com/>
11
11
12
[0] commit cc1965b02d6c ("dt-bindings: mfd: syscon: Add ti,j784s4-pcie-ctrl compatible")
12
Posting next revision for PCIe control node cleanup with minor changes
13
to new overlays added after v1 was posted.
14
15
NOTE: Once the bindings are in the mainline tree, scm_conf will be
16
converted to "simple-bus" compatible which will unblock other
17
items like audio_refclk in scm_conf required for audio support
18
for TI SoC J721S2-EVM (currently giving dtbs_check warnings)
19
20
v1: <https://lore.kernel.org/all/20241016233044.240699-1-afd@ti.com/>
21
22
Changelog v1->v2:
23
- Change property description and add example in the binding
24
- Add changes in additional overlays using pcie*_ctrl node
13
25
14
Andrew Davis (5):
26
Andrew Davis (5):
15
dt-bindings: soc: ti: ti,j721e-system-controller: Add PCIe ctrl
27
dt-bindings: soc: ti: ti,j721e-system-controller: Add PCIe ctrl
16
property
28
property
17
arm64: dts: ti: k3-j721e: Add PCIe ctrl node to scm_conf region
29
arm64: dts: ti: k3-j721e: Add PCIe ctrl node to scm_conf region
18
arm64: dts: ti: k3-j7200: Add PCIe ctrl node to scm_conf region
30
arm64: dts: ti: k3-j7200: Add PCIe ctrl node to scm_conf region
19
arm64: dts: ti: k3-j721s2: Add PCIe ctrl node to scm_conf region
31
arm64: dts: ti: k3-j721s2: Add PCIe ctrl node to scm_conf region
20
arm64: dts: ti: k3-am64: Add PCIe ctrl node to main_conf region
32
arm64: dts: ti: k3-am64: Add PCIe ctrl node to main_conf region
21
33
22
.../soc/ti/ti,j721e-system-controller.yaml | 5 ++++
34
.../soc/ti/ti,j721e-system-controller.yaml | 10 +++++++
23
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 7 ++++-
35
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 7 ++++-
36
.../boot/dts/ti/k3-am642-evm-pcie0-ep.dtso | 2 +-
37
.../ti/k3-am68-sk-base-board-pcie1-ep.dtso | 2 +-
38
.../boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso | 2 +-
24
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++-
39
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++-
25
.../boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso | 2 +-
40
.../boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso | 2 +-
41
.../boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso | 2 +-
26
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 28 ++++++++++++++++---
42
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 28 ++++++++++++++++---
27
.../boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso | 2 +-
43
.../boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso | 2 +-
28
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 7 ++++-
44
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 7 ++++-
29
7 files changed, 49 insertions(+), 9 deletions(-)
45
11 files changed, 58 insertions(+), 13 deletions(-)
30
46
31
--
47
--
32
2.39.2
48
2.34.1
diff view generated by jsdifflib
1
From: Andrew Davis <afd@ti.com>
2
1
Add a pattern property for pcie-ctrl which can be part of this controller.
3
Add a pattern property for pcie-ctrl which can be part of this controller.
2
4
3
Signed-off-by: Andrew Davis <afd@ti.com>
5
Signed-off-by: Andrew Davis <afd@ti.com>
6
[j-choudhary@ti.com: Change description and add example]
7
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
4
---
8
---
5
.../bindings/soc/ti/ti,j721e-system-controller.yaml | 5 +++++
9
.../bindings/soc/ti/ti,j721e-system-controller.yaml | 10 ++++++++++
6
1 file changed, 5 insertions(+)
10
1 file changed, 10 insertions(+)
7
11
8
diff --git a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml
12
diff --git a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml
9
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
10
--- a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml
14
--- a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml
11
+++ b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml
15
+++ b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml
...
...
14
The node corresponding to SoC chip identification.
18
The node corresponding to SoC chip identification.
15
19
16
+ "^pcie-ctrl@[0-9a-f]+$":
20
+ "^pcie-ctrl@[0-9a-f]+$":
17
+ type: object
21
+ type: object
18
+ description:
22
+ description:
19
+ This is the PCIe control region.
23
+ The node corresponding to PCIe control register.
20
+
24
+
21
required:
25
required:
22
- compatible
26
- compatible
23
- reg
27
- reg
28
@@ -XXX,XX +XXX,XX @@ examples:
29
compatible = "ti,am654-chipid";
30
reg = <0x14 0x4>;
31
};
32
+
33
+ pcie0_ctrl: pcie-ctrl@4070 {
34
+ compatible = "ti,j784s4-pcie-ctrl", "syscon";
35
+ reg = <0x4070 0x4>;
36
+ };
37
};
38
...
24
--
39
--
25
2.39.2
40
2.34.1
diff view generated by jsdifflib
1
From: Andrew Davis <afd@ti.com>
2
1
This region is used for controlling the function of the PCIe IP. It is
3
This region is used for controlling the function of the PCIe IP. It is
2
compatible with "ti,j784s4-pcie-ctrl", add this here and use it with
4
compatible with "ti,j784s4-pcie-ctrl", add this here and use it with
3
the PCIe nodes.
5
the PCIe nodes.
4
6
5
Signed-off-by: Andrew Davis <afd@ti.com>
7
Signed-off-by: Andrew Davis <afd@ti.com>
8
[j-choudhary@ti.com: Add changes to k3-j721e-evm-pcie1-ep.dtso]
9
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
6
---
10
---
7
.../boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso | 2 +-
11
.../boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso | 2 +-
12
.../boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso | 2 +-
8
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 28 ++++++++++++++++---
13
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 28 ++++++++++++++++---
9
2 files changed, 25 insertions(+), 5 deletions(-)
14
3 files changed, 26 insertions(+), 6 deletions(-)
10
15
11
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso
16
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso
12
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
13
--- a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso
18
--- a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso
14
+++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso
19
+++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso
...
...
19
-        ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
24
-        ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
20
+        ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
25
+        ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
21
        max-link-speed = <3>;
26
        max-link-speed = <3>;
22
        num-lanes = <1>;
27
        num-lanes = <1>;
23
        power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
28
        power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
29
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso
30
index XXXXXXX..XXXXXXX 100644
31
--- a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso
32
+++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso
33
@@ -XXX,XX +XXX,XX @@ pcie1_ep: pcie-ep@2910000 {
34
        dma-coherent;
35
        phys = <&serdes1_pcie_link>;
36
        phy-names = "pcie-phy";
37
-        ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
38
+        ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
39
    };
40
};
24
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
41
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
25
index XXXXXXX..XXXXXXX 100644
42
index XXXXXXX..XXXXXXX 100644
26
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
43
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
27
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
44
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
28
@@ -XXX,XX +XXX,XX @@ scm_conf: scm-conf@100000 {
45
@@ -XXX,XX +XXX,XX @@ scm_conf: scm-conf@100000 {
...
...
87
+        ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>;
104
+        ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>;
88
        max-link-speed = <3>;
105
        max-link-speed = <3>;
89
        num-lanes = <2>;
106
        num-lanes = <2>;
90
        power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
107
        power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
91
--
108
--
92
2.39.2
109
2.34.1
diff view generated by jsdifflib
1
From: Andrew Davis <afd@ti.com>
2
1
This region is used for controlling the function of the PCIe IP. It is
3
This region is used for controlling the function of the PCIe IP. It is
2
compatible with "ti,j784s4-pcie-ctrl", add this here and use it with
4
compatible with "ti,j784s4-pcie-ctrl", add this here and use it with
3
the PCIe node.
5
the PCIe node.
4
6
5
Signed-off-by: Andrew Davis <afd@ti.com>
7
Signed-off-by: Andrew Davis <afd@ti.com>
8
[j-choudhary@ti.com: Add changes to k3-j7200-evm-pcie1-ep.dtso]
9
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
6
---
10
---
7
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++++-
11
arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso | 2 +-
8
1 file changed, 6 insertions(+), 1 deletion(-)
12
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++++-
13
2 files changed, 7 insertions(+), 2 deletions(-)
9
14
15
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso
16
index XXXXXXX..XXXXXXX 100644
17
--- a/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso
18
+++ b/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso
19
@@ -XXX,XX +XXX,XX @@ pcie1_ep: pcie-ep@2910000 {
20
        dma-coherent;
21
        phys = <&serdes0_pcie_link>;
22
        phy-names = "pcie-phy";
23
-        ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
24
+        ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
25
    };
26
};
10
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
27
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
11
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
12
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
29
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
13
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
30
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
14
@@ -XXX,XX +XXX,XX @@ scm_conf: scm-conf@100000 {
31
@@ -XXX,XX +XXX,XX @@ scm_conf: scm-conf@100000 {
...
...
31
+        ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
48
+        ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
32
        max-link-speed = <3>;
49
        max-link-speed = <3>;
33
        num-lanes = <4>;
50
        num-lanes = <4>;
34
        power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
51
        power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
35
--
52
--
36
2.39.2
53
2.34.1
diff view generated by jsdifflib
1
From: Andrew Davis <afd@ti.com>
2
1
This region is used for controlling the function of the PCIe IP. It is
3
This region is used for controlling the function of the PCIe IP. It is
2
compatible with "ti,j784s4-pcie-ctrl", add this here and use it with
4
compatible with "ti,j784s4-pcie-ctrl", add this here and use it with
3
the PCIe node.
5
the PCIe node.
4
6
5
Signed-off-by: Andrew Davis <afd@ti.com>
7
Signed-off-by: Andrew Davis <afd@ti.com>
8
[j-choudhary@ti.com: Add changes to k3-am68-sk-base-board-pcie1-ep.dtso]
9
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
6
---
10
---
7
arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso | 2 +-
11
arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso | 2 +-
8
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 7 ++++++-
12
arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso | 2 +-
9
2 files changed, 7 insertions(+), 2 deletions(-)
13
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 7 ++++++-
14
3 files changed, 8 insertions(+), 3 deletions(-)
10
15
16
diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso
17
index XXXXXXX..XXXXXXX 100644
18
--- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso
19
+++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso
20
@@ -XXX,XX +XXX,XX @@ pcie1_ep: pcie-ep@2910000 {
21
        dma-coherent;
22
        phys = <&serdes0_pcie_link>;
23
        phy-names = "pcie-phy";
24
-        ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
25
+        ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
26
    };
27
};
11
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso
28
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso
12
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
13
--- a/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso
30
--- a/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso
14
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso
31
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso
15
@@ -XXX,XX +XXX,XX @@ pcie1_ep: pcie-ep@2910000 {
32
@@ -XXX,XX +XXX,XX @@ pcie1_ep: pcie-ep@2910000 {
...
...
45
+        ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
62
+        ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
46
        max-link-speed = <3>;
63
        max-link-speed = <3>;
47
        num-lanes = <4>;
64
        num-lanes = <4>;
48
        power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
65
        power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
49
--
66
--
50
2.39.2
67
2.34.1
diff view generated by jsdifflib
1
From: Andrew Davis <afd@ti.com>
2
1
This region is used for controlling the function of the PCIe IP. It is
3
This region is used for controlling the function of the PCIe IP. It is
2
compatible with "ti,j784s4-pcie-ctrl", add this here and use it with
4
compatible with "ti,j784s4-pcie-ctrl", add this here and use it with
3
the PCIe node.
5
the PCIe node.
4
6
5
Signed-off-by: Andrew Davis <afd@ti.com>
7
Signed-off-by: Andrew Davis <afd@ti.com>
8
[j-choudhary@ti.com: Add changes to k3-am642-evm-pcie0-ep.dtso]
9
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
6
---
10
---
7
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 7 ++++++-
11
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 7 ++++++-
8
1 file changed, 6 insertions(+), 1 deletion(-)
12
arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso | 2 +-
13
2 files changed, 7 insertions(+), 2 deletions(-)
9
14
10
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
15
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
11
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
12
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
17
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
13
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
18
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
...
...
30
-        ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
35
-        ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
31
+        ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
36
+        ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
32
        max-link-speed = <2>;
37
        max-link-speed = <2>;
33
        num-lanes = <1>;
38
        num-lanes = <1>;
34
        power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
39
        power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
40
diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso b/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
41
index XXXXXXX..XXXXXXX 100644
42
--- a/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
43
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
44
@@ -XXX,XX +XXX,XX @@ pcie0_ep: pcie-ep@f102000 {
45
        max-functions = /bits/ 8 <1>;
46
        phys = <&serdes0_pcie_link>;
47
        phy-names = "pcie-phy";
48
-        ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
49
+        ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
50
    };
51
};
35
--
52
--
36
2.39.2
53
2.34.1
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