Series comparison

-[PATCH 0/8] Add devicetree support for SDX75 Modem and IDP
+[PATCH v4 0/5] Add devicetree support for SDX75 Modem and IDP
 Hi,
+Changes in v4:
+ - Addressed some of the dt bindings check mentioned by Krzysztof.
+Changes in v3:
+ - Clubbed all the dt node into a single patch as suggested by Krzysztof.
+ - Removed the applied patch.
+ - Addressed some comments from Konrad and Dmitry.
+Changes in v2:
+ - Added the CPUFreq support patch.
+ - Collected the Acked by tags.
+ - Addressed some minor comments from Konrad.
 This series adds devicetree support for Qualcomm SDX75 platform and IDP
 board. This series functionally depends on GCC and RPMh Clock support
 series [1], and pinctrl support for SDX75 [2] which are under review.
 ...
 Thanks,
 Rohit.
-Imran Shaik (1):
+Rohit Agarwal (5):
   arm64: dts: qcom: Add support for GCC and RPMHCC for SDX75
 Rohit Agarwal (7):
   dt-bindings: arm: qcom: Document SDX75 platform and boards
   dt-bindings: firmware: scm: Add compatible for SDX75
   dt-bindings: interrupt-controller: Add SDX75 PDC compatible
-  dt-bindings: arm-smmu: Add SDX75 SMMU compatible
+  dt-bindings: cpufreq: cpufreq-qcom-hw: Add SDX75 compatible
   arm64: dts: qcom: Add SDX75 platform and IDP board support
-  arm64: dts: qcom: Add QUPv3 UART console node for SDX75
-  arm64: dts: qcom: Enable the QUPv3 UART console for SDX75
  Documentation/devicetree/bindings/arm/qcom.yaml    |   7 +
+ .../bindings/cpufreq/cpufreq-qcom-hw.yaml          |   1 +
  .../devicetree/bindings/firmware/qcom,scm.yaml     |   1 +
  .../bindings/interrupt-controller/qcom,pdc.yaml    |   1 +
- .../devicetree/bindings/iommu/arm,smmu.yaml        |   1 +
  arch/arm64/boot/dts/qcom/Makefile                  |   1 +
- arch/arm64/boot/dts/qcom/sdx75-idp.dts             |  34 ++
+ arch/arm64/boot/dts/qcom/sdx75-idp.dts             |  33 +
- arch/arm64/boot/dts/qcom/sdx75.dtsi                | 618 +++++++++++++++++++++
+ arch/arm64/boot/dts/qcom/sdx75.dtsi                | 670 +++++++++++++++++++++
-files changed, 663 insertions(+)
+files changed, 714 insertions(+)
  create mode 100644 arch/arm64/boot/dts/qcom/sdx75-idp.dts
  create mode 100644 arch/arm64/boot/dts/qcom/sdx75.dtsi
 --
 .7.4

-[PATCH 1/8] dt-bindings: arm: qcom: Document SDX75 platform and boards
+[PATCH v4 1/5] dt-bindings: arm: qcom: Document SDX75 platform and boards
 Document the SDX75 platform binding and also the boards using it.
 Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
 ---
  Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
 file changed, 7 insertions(+)
 diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
 ...

-[PATCH 2/8] dt-bindings: firmware: scm: Add compatible for SDX75
+[PATCH v4 2/5] dt-bindings: firmware: scm: Add compatible for SDX75
 Add devicetree compatible for SCM present in SDX75 platform.
 Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
 ---
  Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 +
 file changed, 1 insertion(+)
 diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
 ...

-[PATCH 3/8] dt-bindings: interrupt-controller: Add SDX75 PDC compatible
+[PATCH v4 3/5] dt-bindings: interrupt-controller: Add SDX75 PDC compatible
 Add device tree bindings for PDC on SDX75 SOC.
 Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
 ---
  Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 +
 file changed, 1 insertion(+)
 diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
 ...

-[PATCH 4/8] dt-bindings: arm-smmu: Add SDX75 SMMU compatible
+[PATCH v4 4/5] dt-bindings: cpufreq: cpufreq-qcom-hw: Add SDX75 compatible
-Add devicetree binding for Qualcomm SDX75 SMMU.
+Add compatible for EPSS CPUFREQ-HW on SDX75.
 Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
+Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 ---
- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 +
+ Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 1 +
 file changed, 1 insertion(+)
-diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
 index XXXXXXX..XXXXXXX 100644
---- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
-+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
++++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
 @@ -XXX,XX +XXX,XX @@ properties:
-               - qcom,sdm845-smmu-500
+               - qcom,sa8775p-cpufreq-epss
-               - qcom,sdx55-smmu-500
+               - qcom,sc7280-cpufreq-epss
-               - qcom,sdx65-smmu-500
+               - qcom,sc8280xp-cpufreq-epss
-+              - qcom,sdx75-smmu-500
++              - qcom,sdx75-cpufreq-epss
-               - qcom,sm6115-smmu-500
+               - qcom,sm6375-cpufreq-epss
-               - qcom,sm6125-smmu-500
+               - qcom,sm8250-cpufreq-epss
-               - qcom,sm6350-smmu-500
+               - qcom,sm8350-cpufreq-epss
 --
 .7.4

-[PATCH 5/8] arm64: dts: qcom: Add SDX75 platform and IDP board support
+[PATCH v4 5/5] arm64: dts: qcom: Add SDX75 platform and IDP board support
 ...
 the Application Processor Sub System (APSS) along with standard Qualcomm
 peripherals like GCC, TLMM, UART, QPIC, and BAM etc... Also, there
 exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem
 etc..
-This commit adds basic devicetree support.
 Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
 ---
  arch/arm64/boot/dts/qcom/Makefile      |   1 +
- arch/arm64/boot/dts/qcom/sdx75-idp.dts |  19 ++
+ arch/arm64/boot/dts/qcom/sdx75-idp.dts |  33 ++
- arch/arm64/boot/dts/qcom/sdx75.dtsi    | 534 +++++++++++++++++++++++++++++++++
+ arch/arm64/boot/dts/qcom/sdx75.dtsi    | 670 +++++++++++++++++++++++++++++++++
-files changed, 554 insertions(+)
+files changed, 704 insertions(+)
  create mode 100644 arch/arm64/boot/dts/qcom/sdx75-idp.dts
  create mode 100644 arch/arm64/boot/dts/qcom/sdx75.dtsi
 diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
 index XXXXXXX..XXXXXXX 100644
 ...
 +#include "sdx75.dtsi"
 +
 +/ {
 +    model = "Qualcomm Technologies, Inc. SDX75 IDP";
 +    compatible = "qcom,sdx75-idp", "qcom,sdx75";
-+    qcom,board-id = <0x2010022 0x302>;
++
-+
++    aliases {
 +        serial0 = &uart1;
 +    };
 +};
 +
 +&chosen {
 +    stdout-path = "serial0:115200n8";
 +};
 +
 +&qupv3_id_0 {
 +    status = "okay";
 +};
 +
 +&tlmm {
 +    gpio-reserved-ranges = <110 6>;
++};
++
++&uart1 {
++    status = "okay";
 +};
 diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 ...
 + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
 + *
 + */
 +
 +#include <dt-bindings/clock/qcom,rpmh.h>
++#include <dt-bindings/clock/qcom,sdx75-gcc.h>
 +#include <dt-bindings/interrupt-controller/arm-gic.h>
 +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
 +
 +/ {
 +    #address-cells = <2>;
 +    #size-cells = <2>;
-+    qcom,msm-id = <556 0x10000>;
 +    interrupt-parent = <&intc>;
 +
 +    chosen: chosen { };
 +
-+    memory {
++    clocks {
-+        device_type = "memory";
++        xo_board: xo-board {
-+        reg = <0 0 0 0>;
++            compatible = "fixed-clock";
-+    };
++            clock-frequency = <76800000>;
-+
++            #clock-cells = <0>;
-+    clocks { };
++        };
 +
 +        sleep_clk: sleep-clk {
 +            compatible = "fixed-clock";
 +            clock-frequency = <32000>;
 +            #clock-cells = <0>;
 +        };
 +    };
 +
 +    cpus {
 +        #address-cells = <2>;
 +        #size-cells = <0>;
 +
 +        CPU0: cpu@0 {
 +            device_type = "cpu";
 +            compatible = "arm,cortex-a55";
 +            reg = <0x0 0x0>;
++            clocks = <&cpufreq_hw 0>;
 +            enable-method = "psci";
 +            power-domains = <&CPU_PD0>;
 +            power-domain-names = "psci";
++            qcom,freq-domain = <&cpufreq_hw 0>;
++            capacity-dmips-mhz = <1024>;
++            dynamic-power-coefficient = <100>;
 +            next-level-cache = <&L2_0>;
++
 +            L2_0: l2-cache {
 +                compatible = "cache";
++                cache-level = <2>;
++                cache-unified;
 +                next-level-cache = <&L3_0>;
 +                L3_0: l3-cache {
 +                    compatible = "cache";
++                    cache-level = <3>;
++                    cache-unified;
 +                };
 +            };
 +        };
 +
 +        CPU1: cpu@100 {
 +            device_type = "cpu";
 +            compatible = "arm,cortex-a55";
 +            reg = <0x0 0x100>;
++            clocks = <&cpufreq_hw 0>;
 +            enable-method = "psci";
 +            power-domains = <&CPU_PD1>;
 +            power-domain-names = "psci";
++            qcom,freq-domain = <&cpufreq_hw 0>;
++            capacity-dmips-mhz = <1024>;
++            dynamic-power-coefficient = <100>;
 +            next-level-cache = <&L2_100>;
++
 +            L2_100: l2-cache {
 +                compatible = "cache";
++                cache-level = <2>;
++                cache-unified;
 +                next-level-cache = <&L3_0>;
 +            };
 +        };
 +
 +        CPU2: cpu@200 {
 +            device_type = "cpu";
 +            compatible = "arm,cortex-a55";
 +            reg = <0x0 0x200>;
++            clocks = <&cpufreq_hw 0>;
 +            enable-method = "psci";
 +            power-domains = <&CPU_PD2>;
 +            power-domain-names = "psci";
++            qcom,freq-domain = <&cpufreq_hw 0>;
++            capacity-dmips-mhz = <1024>;
++            dynamic-power-coefficient = <100>;
 +            next-level-cache = <&L2_200>;
++
 +            L2_200: l2-cache {
 +                compatible = "cache";
++                cache-level = <2>;
++                cache-unified;
 +                next-level-cache = <&L3_0>;
 +            };
 +        };
 +
 +        CPU3: cpu@300 {
 +            device_type = "cpu";
 +            compatible = "arm,cortex-a55";
 +            reg = <0x0 0x300>;
++            clocks = <&cpufreq_hw 0>;
 +            enable-method = "psci";
 +            power-domains = <&CPU_PD3>;
 +            power-domain-names = "psci";
++            qcom,freq-domain = <&cpufreq_hw 0>;
++            capacity-dmips-mhz = <1024>;
++            dynamic-power-coefficient = <100>;
 +            next-level-cache = <&L2_300>;
++
 +            L2_300: l2-cache {
 +                compatible = "cache";
++                cache-level = <2>;
++                cache-unified;
 +                next-level-cache = <&L3_0>;
 +            };
 +        };
 +
 +        cpu-map {
 ...
 +                core3 {
 +                    cpu = <&CPU3>;
 +                };
 +            };
 +        };
-+    };
++
-+
++        idle-states {
-+    idle-states {
++            entry-method = "psci";
-+        entry-method = "psci";
++
-+
++            CPU_OFF: cpu-sleep-0 {
-+        CPU_OFF: cpu-sleep-0 {
++                compatible = "arm,idle-state";
-+            compatible = "arm,idle-state";
++                entry-latency-us = <235>;
-+            entry-latency-us = <235>;
++                exit-latency-us = <428>;
-+            exit-latency-us = <428>;
++                min-residency-us = <1774>;
-+            min-residency-us = <1774>;
++                arm,psci-suspend-param = <0x40000003>;
-+            arm,psci-suspend-param = <0x40000003>;
++                local-timer-stop;
-+            local-timer-stop;
++            };
-+        };
++
-+
++            CPU_RAIL_OFF: cpu-rail-sleep-1 {
-+        CPU_RAIL_OFF: cpu-rail-sleep-1 {
++                compatible = "arm,idle-state";
-+            compatible = "arm,idle-state";
++                entry-latency-us = <800>;
-+            entry-latency-us = <800>;
++                exit-latency-us = <750>;
-+            exit-latency-us = <750>;
++                min-residency-us = <4090>;
-+            min-residency-us = <4090>;
++                arm,psci-suspend-param = <0x40000004>;
-+            arm,psci-suspend-param = <0x40000004>;
++                local-timer-stop;
-+            local-timer-stop;
++            };
-+        };
++
-+
++        };
-+    };
++
-+
++        domain-idle-states {
-+    domain-idle-states {
++            CLUSTER_SLEEP_0: cluster-sleep-0 {
-+        CLUSTER_SLEEP_0: cluster-sleep-0 {
++                compatible = "domain-idle-state";
-+            compatible = "domain-idle-state";
++                arm,psci-suspend-param = <0x41000044>;
-+            arm,psci-suspend-param = <0x41000044>;
++                entry-latency-us = <1050>;
-+            entry-latency-us = <1050>;
++                exit-latency-us = <2500>;
-+            exit-latency-us = <2500>;
++                min-residency-us = <5309>;
-+            min-residency-us = <5309>;
++            };
-+        };
++
-+
++            CLUSTER_SLEEP_1: cluster-sleep-1 {
-+        CLUSTER_SLEEP_1: cluster-sleep-1 {
++                compatible = "domain-idle-state";
-+            compatible = "domain-idle-state";
++                arm,psci-suspend-param = <0x41001344>;
-+            arm,psci-suspend-param = <0x4100b344>;
++                entry-latency-us = <2761>;
-+            entry-latency-us = <2793>;
++                exit-latency-us = <3964>;
-+            exit-latency-us = <4023>;
++                min-residency-us = <8467>;
-+            min-residency-us = <9826>;
++            };
-+        };
++
-+
++            CLUSTER_SLEEP_2: cluster-sleep-2 {
-+        CX_RET: cx-ret {
++                compatible = "domain-idle-state";
-+            compatible = "domain-idle-state";
++                arm,psci-suspend-param = <0x4100b344>;
-+            arm,psci-suspend-param = <0x41001344>;
++                entry-latency-us = <2793>;
-+            entry-latency-us = <2761>;
++                exit-latency-us = <4023>;
-+            exit-latency-us = <3964>;
++                min-residency-us = <9826>;
-+            min-residency-us = <8467>;
++            };
 +        };
 +    };
 +
 +    firmware {
 +        scm: scm {
 +            compatible = "qcom,scm-sdx75", "qcom,scm";
 +        };
 +    };
 +
 +    memory@80000000 {
 +        device_type = "memory";
 +        reg = <0x0 0x80000000 0x0 0x0>;
 +    };
 +
 +    pmu {
 +        compatible = "arm,armv8-pmuv3";
 +        interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 +    };
 +
 +    psci {
 +        compatible = "arm,psci-1.0";
 +        method = "smc";
 ...
 +            domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
 +        };
 +
 +        CLUSTER_PD: power-domain-cpu-cluster0 {
 +            #power-domain-cells = <0>;
-+            domain-idle-states = <&CLUSTER_SLEEP_0 &CX_RET &CLUSTER_SLEEP_1>;
++            domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>;
 +        };
 +    };
 +
 +    firmware {
 +        scm: scm {
 +            compatible = "qcom,scm-sdx75", "qcom,scm";
 +        };
 +    };
 +
 +    pmu {
 +        compatible = "arm,armv8-pmuv3";
 +        interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 +    };
 +
 +    reserved-memory {
 +        #address-cells = <2>;
 +        #size-cells = <2>;
 +        ranges;
 +
-+        gunyah_hyp_mem: memory@80000000 {
++        gunyah_hyp_mem: gunyah-hyp@80000000 {
 +            reg = <0x0 0x80000000 0x0 0x800000>;
 +            no-map;
 +        };
 +
-+        hyp_elf_package_mem: memory@80800000 {
++        hyp_elf_package_mem: hyp-elf-package@80800000 {
 +            reg = <0x0 0x80800000 0x0 0x200000>;
 +            no-map;
 +        };
 +
-+        access_control_db_mem: memory@81380000 {
++        access_control_db_mem: access-control-db@81380000 {
 +            reg = <0x0 0x81380000 0x0 0x80000>;
 +            no-map;
 +        };
 +
-+        qteetz_mem: memory@814e0000 {
++        qteetz_mem: qteetz@814e0000 {
 +            reg = <0x0 0x814e0000 0x0 0x2a0000>;
 +            no-map;
 +        };
 +
-+        trusted_apps_mem: memory@81780000 {
++        trusted_apps_mem: trusted-apps@81780000 {
 +            reg = <0x0 0x81780000 0x0 0xa00000>;
 +            no-map;
 +        };
 +
-+        xbl_ramdump_mem: memory@87a00000 {
++        xbl_ramdump_mem: xbl-ramdump@87a00000 {
 +            reg = <0x0 0x87a00000 0x0 0x1c0000>;
 +            no-map;
 +        };
 +
-+        cpucp_fw_mem: memory@87c00000 {
++        cpucp_fw_mem: cpucp-fw@87c00000 {
 +            reg = <0x0 0x87c00000 0x0 0x100000>;
 +            no-map;
 +        };
 +
-+        xbl_dtlog_mem: memory@87d00000 {
++        xbl_dtlog_mem: xbl-dtlog@87d00000 {
 +            reg = <0x0 0x87d00000 0x0 0x40000>;
 +            no-map;
 +        };
 +
-+        xbl_sc_mem: memory@87d40000 {
++        xbl_sc_mem: xbl-sc@87d40000 {
 +            reg = <0x0 0x87d40000 0x0 0x40000>;
 +            no-map;
 +        };
 +
-+        modem_efs_shared_mem: memory@87d80000 {
++        modem_efs_shared_mem: modem-efs-shared@87d80000 {
 +            reg = <0x0 0x87d80000 0x0 0x10000>;
 +            no-map;
 +        };
 +
-+        aop_image_mem: memory@87e00000 {
++        aop_image_mem: aop-image@87e00000 {
 +            reg = <0x0 0x87e00000 0x0 0x20000>;
 +            no-map;
 +        };
 +
-+        smem_mem: memory@87e20000 {
++        smem_mem: smem@87e20000 {
 +            reg = <0x0 0x87e20000 0x0 0xc0000>;
 +            no-map;
 +        };
 +
-+        aop_cmd_db_mem: memory@87ee0000 {
++        aop_cmd_db_mem: aop-cmd-db@87ee0000 {
 +            compatible = "qcom,cmd-db";
 +            reg = <0x0 0x87ee0000 0x0 0x20000>;
 +            no-map;
 +        };
 +
-+        aop_config_mem: memory@87f00000 {
++        aop_config_mem: aop-config@87f00000 {
 +            reg = <0x0 0x87f00000 0x0 0x20000>;
 +            no-map;
 +        };
 +
-+        ipa_fw_mem: memory@87f20000 {
++        ipa_fw_mem: ipa-fw@87f20000 {
 +            reg = <0x0 0x87f20000 0x0 0x10000>;
 +            no-map;
 +        };
 +
-+        secdata_mem: memory@87f30000 {
++        secdata_mem: secdata@87f30000 {
 +            reg = <0x0 0x87f30000 0x0 0x1000>;
 +            no-map;
 +        };
 +
-+        tme_crashdump_mem: memory@87f31000 {
++        tme_crashdump_mem: tme-crashdump@87f31000 {
 +            reg = <0x0 0x87f31000 0x0 0x40000>;
 +            no-map;
 +        };
 +
-+        tme_log_mem: memory@87f71000 {
++        tme_log_mem: tme-log@87f71000 {
 +            reg = <0x0 0x87f71000 0x0 0x4000>;
 +            no-map;
 +        };
 +
-+        uefi_log_mem: memory@87f75000 {
++        uefi_log_mem: uefi-log@87f75000 {
 +            reg = <0x0 0x87f75000 0x0 0x10000>;
 +            no-map;
 +        };
 +
-+        qdss_mem: memory@88800000 {
++        qdss_mem: qdss@88800000 {
 +            reg = <0x0 0x88800000 0x0 0x300000>;
 +            no-map;
 +        };
 +
-+        audio_heap_mem: memory@88b00000 {
++        audio_heap_mem: audio-heap@88b00000 {
 +            compatible = "shared-dma-pool";
 +            reg = <0x0 0x88b00000 0x0 0x400000>;
 +            no-map;
 +        };
 +
-+        mpss_dsmharq_mem: memory@88f00000 {
++        mpss_dsmharq_mem: mpss-dsmharq@88f00000 {
 +            reg = <0x0 0x88f00000 0x0 0x5080000>;
 +            no-map;
 +        };
 +
-+        q6_mpss_dtb_mem: memory@8df80000 {
++        q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 {
 +            reg = <0x0 0x8df80000 0x0 0x80000>;
 +            no-map;
 +        };
 +
-+        mpssadsp_mem: memory@8e000000 {
++        mpssadsp_mem: mpssadsp@8e000000 {
 +            reg = <0x0 0x8e000000 0x0 0xf400000>;
 +            no-map;
 +        };
 +
-+        gunyah_trace_buffer_mem: memory@bdb00000 {
++        gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 {
 +            reg = <0x0 0xbdb00000 0x0 0x2000000>;
 +            no-map;
 +        };
 +
-+        smmu_debug_buf_mem: memory@bfb00000 {
++        smmu_debug_buf_mem: smmu-debug-buf@bfb00000 {
 +            reg = <0x0 0xbfb00000 0x0 0x100000>;
 +            no-map;
 +        };
 +
-+        hyp_smmu_s2_pt_mem: memory@bfc00000 {
++        hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 {
 +            reg = <0x0 0xbfc00000 0x0 0x400000>;
 +            no-map;
 +        };
 +    };
 +
 ...
 +        memory-region = <&smem_mem>;
 +        hwlocks = <&tcsr_mutex 3>;
 +    };
 +
 +    soc: soc {
++        compatible = "simple-bus";
 +        #address-cells = <2>;
 +        #size-cells = <2>;
-+        ranges;
++        ranges = <0 0 0 0 0x10 0>;
-+        compatible = "simple-bus";
++        dma-ranges = <0 0 0 0 0x10 0>;
 +
 +        gcc: clock-controller@80000 {
 +            compatible = "qcom,sdx75-gcc";
 +            reg = <0x0 0x0080000 0x0 0x1f7400>;
 +            clocks = <&rpmhcc RPMH_CXO_CLK>,
 +                 <&sleep_clk>,
 +                 <0>,
 +                 <0>,
 +                 <0>,
 +                 <0>,
 +                 <0>,
 +                 <0>,
 +                 <0>,
 +                 <0>,
 +                 <0>,
 +                 <0>,
 +                 <0>,
 +                 <0>,
 +                 <0>;
 +            #clock-cells = <1>;
 +            #reset-cells = <1>;
 +            #power-domain-cells = <1>;
 +        };
 +
 +        qupv3_id_0: geniqup@9c0000 {
 +            compatible = "qcom,geni-se-qup";
 +            reg = <0x0 0x009c0000 0x0 0x2000>;
 +            clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 +                 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 +            clock-names = "m-ahb",
 +                      "s-ahb";
 +            iommus = <&apps_smmu 0xe3 0x0>;
 +            #address-cells = <2>;
 +            #size-cells = <2>;
 +            ranges;
 +            status = "disabled";
 +
 +            uart1: serial@984000 {
 +                compatible = "qcom,geni-debug-uart";
 +                reg = <0x0 0x00984000 0x0 0x4000>;
 +                clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 +                clock-names = "se";
 +                interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
 +                pinctrl-0 = <&qupv3_se1_2uart_active>;
 +                pinctrl-1 = <&qupv3_se1_2uart_sleep>;
 +                pinctrl-names = "default",
 +                        "sleep";
 +                status = "disabled";
 +            };
 +        };
 +
 +        tcsr_mutex: hwlock@1f40000 {
 +            compatible = "qcom,tcsr-mutex";
 +            reg = <0x0 0x01f40000 0x0 0x40000>;
 +            #hwlock-cells = <1>;
 ...
 +            #gpio-cells = <2>;
 +            gpio-ranges = <&tlmm 0 0 133>;
 +            interrupt-controller;
 +            #interrupt-cells = <2>;
 +            wakeup-parent = <&pdc>;
++
++            qupv3_se1_2uart_active: qupv3-se1-2uart-active-state {
++                tx-pins {
++                    pins = "gpio12";
++                    function = "qup_se1_l2_mira";
++                    drive-strength= <2>;
++                    bias-disable;
++                };
++
++                rx-pins {
++                    pins = "gpio13";
++                    function = "qup_se1_l3_mira";
++                    drive-strength= <2>;
++                    bias-disable;
++                };
++            };
++
++            qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state {
++                pins = "gpio12", "gpio13";
++                function = "gpio";
++                drive-strength = <2>;
++                bias-pull-down;
++            };
 +        };
 +
 +        apps_smmu: iommu@15000000 {
-+            compatible = "qcom,sdx75-smmu-500", "arm,mmu-500";
++            compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500";
 +            reg = <0x0 0x15000000 0x0 0x40000>;
 +            #iommu-cells = <2>;
 +            #global-interrupts = <2>;
++            dma-coherent;
 +            interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 +                     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 +                     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 +                     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 +                     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
 ...
 +            interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 +        };
 +
 +        timer@17420000 {
 +            compatible = "arm,armv7-timer-mem";
-+            #address-cells = <2>;
-+            #size-cells = <2>;
-+            ranges;
 +            reg = <0x0 0x17420000 0x0 0x1000>;
-+            clock-frequency = <19200000>;
++            #address-cells = <1>;
 +            #size-cells = <1>;
 +            ranges = <0 0 0 0x20000000>;
 +
 +            frame@17421000 {
++                reg = <0x17421000 0x1000>,
++                      <0x17422000 0x1000>;
 +                frame-number = <0>;
 +                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 +                         <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
-+                reg = <0x0 0x17421000 0x0 0x1000>,
-+                      <0x0 0x17422000 0x0 0x1000>;
 +            };
 +
 +            frame@17423000 {
++                reg = <0x17423000 0x1000>;
 +                frame-number = <1>;
 +                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
-+                reg = <0x0 0x17425000 0x0 0x1000>;
 +                status = "disabled";
 +            };
 +
 +            frame@17425000 {
++                reg = <0x17425000 0x1000>;
 +                frame-number = <2>;
 +                interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-+                reg = <0x0 0x17425000 0x0 0x1000>;
 +                status = "disabled";
 +            };
 +
 +            frame@17427000 {
++                reg = <0x17427000 0x1000>;
 +                frame-number = <3>;
 +                interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
-+                reg = <0x0 0x17427000 0x0 0x1000>;
 +                status = "disabled";
 +            };
 +
 +            frame@17429000 {
++                reg = <0x17429000 0x1000>;
 +                frame-number = <4>;
 +                interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
-+                reg = <0x0 0x17429000 0x0 0x1000>;
 +                status = "disabled";
 +            };
 +
 +            frame@1742b000 {
++                reg = <0x1742b000 0x1000>;
 +                frame-number = <5>;
 +                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
-+                reg = <0x0 0x1742b000 0x0 0x1000>;
 +                status = "disabled";
 +            };
 +
 +            frame@1742d000 {
++                reg = <0x1742d000 0x1000>;
 +                frame-number = <6>;
 +                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-+                reg = <0x0 0x1742d000 0x0 0x1000>;
 +                status = "disabled";
 +            };
 +        };
 +
 +        apps_rsc: rsc@17a00000 {
 ...
 +            qcom,tcs-config = <ACTIVE_TCS    3>,
 +                      <SLEEP_TCS     2>,
 +                      <WAKE_TCS      2>,
 +                      <CONTROL_TCS   0>;
 +
-+            apps_bcm_voter: bcm_voter {
++            apps_bcm_voter: bcm-voter {
 +                compatible = "qcom,bcm-voter";
 +            };
++
++            rpmhcc: clock-controller {
++                compatible = "qcom,sdx75-rpmh-clk";
++                clocks = <&xo_board>;
++                clock-names = "xo";
++                #clock-cells = <1>;
++            };
++        };
++
++        cpufreq_hw: cpufreq@17d91000 {
++            compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss";
++            reg = <0x0 0x17d91000 0x0 0x1000>;
++            reg-names = "freq-domain0";
++            clocks = <&rpmhcc RPMH_CXO_CLK>,
++                 <&gcc GPLL0>;
++            clock-names = "xo",
++                      "alternate";
++            interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++            interrupt-names = "dcvsh-irq-0";
++            #freq-domain-cells = <1>;
++            #clock-cells = <1>;
 +        };
 +    };
 +
 +    timer {
 +        compatible = "arm,armv8-timer";
 +        interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 +                 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 +                 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 +                 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
-+        clock-frequency = <19200000>;
 +    };
 +};
 --
 .7.4

-[PATCH 6/8] arm64: dts: qcom: Add support for GCC and RPMHCC for SDX75
+Deleted patch
-From: Imran Shaik <quic_imrashai@quicinc.com>
-Add support for GCC and RPMHCC clock nodes for SDX75 platform.
-Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
-Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
----
- arch/arm64/boot/dts/qcom/sdx75.dtsi | 37 ++++++++++++++++++++++++++++++++++++-
-file changed, 36 insertions(+), 1 deletion(-)
-diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
-index XXXXXXX..XXXXXXX 100644
---- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
-+++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
-@@ -XXX,XX +XXX,XX @@
-  */
- #include <dt-bindings/clock/qcom,rpmh.h>
-+#include <dt-bindings/clock/qcom,sdx75-gcc.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/soc/qcom,rpmh-rsc.h>
-@@ -XXX,XX +XXX,XX @@
-         reg = <0 0 0 0>;
-     };
--    clocks { };
-+    clocks {
-+        xo_board: xo_board {
-+            compatible = "fixed-clock";
-+            clock-frequency = <76800000>;
-+            clock-output-names = "xo_board";
-+            #clock-cells = <0>;
-+        };
-+
-+        sleep_clk: sleep_clk {
-+            compatible = "fixed-clock";
-+            clock-frequency = <32000>;
-+            clock-output-names = "sleep_clk";
-+            #clock-cells = <0>;
-+        };
-+    };
-     cpus {
-         #address-cells = <2>;
-@@ -XXX,XX +XXX,XX @@
-         ranges;
-         compatible = "simple-bus";
-+        gcc: clock-controller@80000 {
-+            compatible = "qcom,sdx75-gcc";
-+            reg = <0x0 0x0080000 0x0 0x1f7400>;
-+            clocks = <&rpmhcc RPMH_CXO_CLK>,
-+                 <&sleep_clk>;
-+            clock-names = "bi_tcxo",
-+                      "sleep_clk";
-+            #clock-cells = <1>;
-+            #reset-cells = <1>;
-+            #power-domain-cells = <1>;
-+        };
-+
-         tcsr_mutex: hwlock@1f40000 {
-             compatible = "qcom,tcsr-mutex";
-             reg = <0x0 0x01f40000 0x0 0x40000>;
-@@ -XXX,XX +XXX,XX @@
-             apps_bcm_voter: bcm_voter {
-                 compatible = "qcom,bcm-voter";
-             };
-+
-+            rpmhcc: clock-controller {
-+                compatible = "qcom,sdx75-rpmh-clk";
-+                clocks = <&xo_board>;
-+                clock-names = "xo";
-+                #clock-cells = <1>;
-+            };
-+
-         };
-     };
---
-.7.4

-[PATCH 7/8] arm64: dts: qcom: Add QUPv3 UART console node for SDX75
+Deleted patch
-Add the debug uart console node in devicetree.
-Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
----
- arch/arm64/boot/dts/qcom/sdx75.dtsi | 49 +++++++++++++++++++++++++++++++++++++
-file changed, 49 insertions(+)
-diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
-index XXXXXXX..XXXXXXX 100644
---- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
-+++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
-@@ -XXX,XX +XXX,XX @@
-             #power-domain-cells = <1>;
-         };
-+        qupv3_id_0: geniqup@9c0000 {
-+            compatible = "qcom,geni-se-qup";
-+            reg = <0x0 0x009c0000 0x0 0x2000>;
-+            clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
-+                 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
-+            clock-names = "m-ahb",
-+                      "s-ahb";
-+            iommus = <&apps_smmu 0xe3 0x0>;
-+            #address-cells = <2>;
-+            #size-cells = <2>;
-+            ranges;
-+            status = "disabled";
-+
-+            uart1: serial@984000 {
-+                compatible = "qcom,geni-debug-uart";
-+                reg = <0x0 0x00984000 0x0 0x4000>;
-+                clock-names = "se";
-+                clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
-+                interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
-+                pinctrl-0 = <&qupv3_se1_2uart_tx_active>,
-+                        <&qupv3_se1_2uart_rx_active>;
-+                pinctrl-1 = <&qupv3_se1_2uart_sleep>;
-+                pinctrl-names = "default",
-+                        "sleep";
-+                status = "disabled";
-+            };
-+        };
-+
-         tcsr_mutex: hwlock@1f40000 {
-             compatible = "qcom,tcsr-mutex";
-             reg = <0x0 0x01f40000 0x0 0x40000>;
-@@ -XXX,XX +XXX,XX @@
-             interrupt-controller;
-             #interrupt-cells = <2>;
-             wakeup-parent = <&pdc>;
-+
-+            qupv3_se1_2uart_tx_active: qupv3-se1-2uart-tx-active-state {
-+                pins = "gpio12";
-+                function = "qup_se1_l2_mira";
-+                drive-strength= <2>;
-+                bias-disable;
-+            };
-+
-+            qupv3_se1_2uart_rx_active: qupv3-se1-2uart-rx-active-state {
-+                pins = "gpio13";
-+                function = "qup_se1_l3_mira";
-+                drive-strength= <2>;
-+                bias-disable;
-+            };
-+
-+            qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state {
-+                pins = "gpio12", "gpio13";
-+                function = "gpio";
-+                drive-strength = <2>;
-+                bias-pull-down;
-+            };
-         };
-         apps_smmu: iommu@15000000 {
---
-.7.4

-[PATCH 8/8] arm64: dts: qcom: Enable the QUPv3 UART console for SDX75
+Deleted patch
-Enable the debug uart console for the SDX75 IDP board.
-Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
----
- arch/arm64/boot/dts/qcom/sdx75-idp.dts | 15 +++++++++++++++
-file changed, 15 insertions(+)
-diff --git a/arch/arm64/boot/dts/qcom/sdx75-idp.dts b/arch/arm64/boot/dts/qcom/sdx75-idp.dts
-index XXXXXXX..XXXXXXX 100644
---- a/arch/arm64/boot/dts/qcom/sdx75-idp.dts
-+++ b/arch/arm64/boot/dts/qcom/sdx75-idp.dts
-@@ -XXX,XX +XXX,XX @@
-     compatible = "qcom,sdx75-idp", "qcom,sdx75";
-     qcom,board-id = <0x2010022 0x302>;
-+    aliases {
-+        serial0 = &uart1;
-+    };
-+};
-+
-+&chosen {
-+    stdout-path = "serial0:115200n8";
-+};
-+
-+&qupv3_id_0 {
-+    status = "okay";
- };
- &tlmm {
-     gpio-reserved-ranges = <110 6>;
- };
-+
-+&uart1 {
-+    status = "okay";
-+};
---
-.7.4

Hi,

This series adds devicetree support for Qualcomm SDX75 platform and IDP
board. This series functionally depends on GCC and RPMh Clock support
series [1], and pinctrl support for SDX75 [2] which are under review.

With this current devicetree support, the IDP can boot into initramfsshell.

[1] https://lore.kernel.org/lkml/20230419133013.2563-3-quic_tdas@quicinc.com/
[2] https://lore.kernel.org/all/1684409015-25196-1-git-send-email-quic_rohiagar@quicinc.com/

Thanks,
Rohit.

Imran Shaik (1):
  arm64: dts: qcom: Add support for GCC and RPMHCC for SDX75

Rohit Agarwal (7):
  dt-bindings: arm: qcom: Document SDX75 platform and boards
  dt-bindings: firmware: scm: Add compatible for SDX75
  dt-bindings: interrupt-controller: Add SDX75 PDC compatible
  dt-bindings: arm-smmu: Add SDX75 SMMU compatible
  arm64: dts: qcom: Add SDX75 platform and IDP board support
  arm64: dts: qcom: Add QUPv3 UART console node for SDX75
  arm64: dts: qcom: Enable the QUPv3 UART console for SDX75

Documentation/devicetree/bindings/arm/qcom.yaml    |   7 +
 .../devicetree/bindings/firmware/qcom,scm.yaml     |   1 +
 .../bindings/interrupt-controller/qcom,pdc.yaml    |   1 +
 .../devicetree/bindings/iommu/arm,smmu.yaml        |   1 +
 arch/arm64/boot/dts/qcom/Makefile                  |   1 +
 arch/arm64/boot/dts/qcom/sdx75-idp.dts             |  34 ++
 arch/arm64/boot/dts/qcom/sdx75.dtsi                | 618 +++++++++++++++++++++
 7 files changed, 663 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sdx75-idp.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sdx75.dtsi

-- 
2.7.4

Document the SDX75 platform binding and also the boards using it.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index XXXXXXX..XXXXXXX 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -XXX,XX +XXX,XX @@ description: |
         sdm845
         sdx55
         sdx65
+        sdx75
         sm4250
         sm6115
         sm6115p
@@ -XXX,XX +XXX,XX @@ properties:
 
       - items:
           - enum:
+              - qcom,sdx75-idp
+          - const: qcom,sdx75
+
+      - items:
+          - enum:
               - qcom,ipq6018-cp01
               - qcom,ipq6018-cp01-c1
           - const: qcom,ipq6018
@@ -XXX,XX +XXX,XX @@ allOf:
               - qcom,sdm845
               - qcom,sdx55
               - qcom,sdx65
+              - qcom,sdx75
               - qcom,sm4250
               - qcom,sm6115
               - qcom,sm6125
-- 
2.7.4

Add basic devicetree support for SDX75 platform and IDP board from
Qualcomm. The SDX75 platform features an ARM Cortex A55 CPU which forms
the Application Processor Sub System (APSS) along with standard Qualcomm
peripherals like GCC, TLMM, UART, QPIC, and BAM etc... Also, there
exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem
etc..

This commit adds basic devicetree support.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 arch/arm64/boot/dts/qcom/Makefile      |   1 +
 arch/arm64/boot/dts/qcom/sdx75-idp.dts |  19 ++
 arch/arm64/boot/dts/qcom/sdx75.dtsi    | 534 +++++++++++++++++++++++++++++++++
 3 files changed, 554 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sdx75-idp.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sdx75.dtsi

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index XXXXXXX..XXXXXXX 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -XXX,XX +XXX,XX @@ dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-xiaomi-polaris.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-shift-axolotl.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm850-lenovo-yoga-c630.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm850-samsung-w737.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= sdx75-idp.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm4250-oneplus-billie2.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm6115p-lenovo-j606f.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm6125-sony-xperia-seine-pdx201.dtb
diff --git a/arch/arm64/boot/dts/qcom/sdx75-idp.dts b/arch/arm64/boot/dts/qcom/sdx75-idp.dts
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdx75-idp.dts
@@ -XXX,XX +XXX,XX @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "sdx75.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SDX75 IDP";
+	compatible = "qcom,sdx75-idp", "qcom,sdx75";
+	qcom,board-id = <0x2010022 0x302>;
+
+};
+
+&tlmm {
+	gpio-reserved-ranges = <110 6>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
@@ -XXX,XX +XXX,XX @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * SDX75 SoC device tree source
+ *
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ */
+
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	qcom,msm-id = <556 0x10000>;
+	interrupt-parent = <&intc>;
+
+	chosen: chosen { };
+
+	memory {
+		device_type = "memory";
+		reg = <0 0 0 0>;
+	};
+
+	clocks { };
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			power-domains = <&CPU_PD0>;
+			power-domain-names = "psci";
+			next-level-cache = <&L2_0>;
+			L2_0: l2-cache {
+				compatible = "cache";
+				next-level-cache = <&L3_0>;
+				L3_0: l3-cache {
+					compatible = "cache";
+				};
+			};
+		};
+
+		CPU1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			power-domains = <&CPU_PD1>;
+			power-domain-names = "psci";
+			next-level-cache = <&L2_100>;
+			L2_100: l2-cache {
+				compatible = "cache";
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+			power-domains = <&CPU_PD2>;
+			power-domain-names = "psci";
+			next-level-cache = <&L2_200>;
+			L2_200: l2-cache {
+				compatible = "cache";
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+			power-domains = <&CPU_PD3>;
+			power-domain-names = "psci";
+			next-level-cache = <&L2_300>;
+			L2_300: l2-cache {
+				compatible = "cache";
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+
+				core2 {
+					cpu = <&CPU2>;
+				};
+
+				core3 {
+					cpu = <&CPU3>;
+				};
+			};
+		};
+	};
+
+	idle-states {
+		entry-method = "psci";
+
+		CPU_OFF: cpu-sleep-0 {
+			compatible = "arm,idle-state";
+			entry-latency-us = <235>;
+			exit-latency-us = <428>;
+			min-residency-us = <1774>;
+			arm,psci-suspend-param = <0x40000003>;
+			local-timer-stop;
+		};
+
+		CPU_RAIL_OFF: cpu-rail-sleep-1 {
+			compatible = "arm,idle-state";
+			entry-latency-us = <800>;
+			exit-latency-us = <750>;
+			min-residency-us = <4090>;
+			arm,psci-suspend-param = <0x40000004>;
+			local-timer-stop;
+		};
+
+	};
+
+	domain-idle-states {
+		CLUSTER_SLEEP_0: cluster-sleep-0 {
+			compatible = "domain-idle-state";
+			arm,psci-suspend-param = <0x41000044>;
+			entry-latency-us = <1050>;
+			exit-latency-us = <2500>;
+			min-residency-us = <5309>;
+		};
+
+		CLUSTER_SLEEP_1: cluster-sleep-1 {
+			compatible = "domain-idle-state";
+			arm,psci-suspend-param = <0x4100b344>;
+			entry-latency-us = <2793>;
+			exit-latency-us = <4023>;
+			min-residency-us = <9826>;
+		};
+
+		CX_RET: cx-ret {
+			compatible = "domain-idle-state";
+			arm,psci-suspend-param = <0x41001344>;
+			entry-latency-us = <2761>;
+			exit-latency-us = <3964>;
+			min-residency-us = <8467>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+
+		CPU_PD0: power-domain-cpu0 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
+		};
+
+		CPU_PD1: power-domain-cpu1 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
+		};
+
+		CPU_PD2: power-domain-cpu2 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
+		};
+
+		CPU_PD3: power-domain-cpu3 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
+		};
+
+		CLUSTER_PD: power-domain-cpu-cluster0 {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&CLUSTER_SLEEP_0 &CX_RET &CLUSTER_SLEEP_1>;
+		};
+	};
+
+	firmware {
+		scm: scm {
+			compatible = "qcom,scm-sdx75", "qcom,scm";
+		};
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		gunyah_hyp_mem: memory@80000000 {
+			reg = <0x0 0x80000000 0x0 0x800000>;
+			no-map;
+		};
+
+		hyp_elf_package_mem: memory@80800000 {
+			reg = <0x0 0x80800000 0x0 0x200000>;
+			no-map;
+		};
+
+		access_control_db_mem: memory@81380000 {
+			reg = <0x0 0x81380000 0x0 0x80000>;
+			no-map;
+		};
+
+		qteetz_mem: memory@814e0000 {
+			reg = <0x0 0x814e0000 0x0 0x2a0000>;
+			no-map;
+		};
+
+		trusted_apps_mem: memory@81780000 {
+			reg = <0x0 0x81780000 0x0 0xa00000>;
+			no-map;
+		};
+
+		xbl_ramdump_mem: memory@87a00000 {
+			reg = <0x0 0x87a00000 0x0 0x1c0000>;
+			no-map;
+		};
+
+		cpucp_fw_mem: memory@87c00000 {
+			reg = <0x0 0x87c00000 0x0 0x100000>;
+			no-map;
+		};
+
+		xbl_dtlog_mem: memory@87d00000 {
+			reg = <0x0 0x87d00000 0x0 0x40000>;
+			no-map;
+		};
+
+		xbl_sc_mem: memory@87d40000 {
+			reg = <0x0 0x87d40000 0x0 0x40000>;
+			no-map;
+		};
+
+		modem_efs_shared_mem: memory@87d80000 {
+			reg = <0x0 0x87d80000 0x0 0x10000>;
+			no-map;
+		};
+
+		aop_image_mem: memory@87e00000 {
+			reg = <0x0 0x87e00000 0x0 0x20000>;
+			no-map;
+		};
+
+		smem_mem: memory@87e20000 {
+			reg = <0x0 0x87e20000 0x0 0xc0000>;
+			no-map;
+		};
+
+		aop_cmd_db_mem: memory@87ee0000 {
+			compatible = "qcom,cmd-db";
+			reg = <0x0 0x87ee0000 0x0 0x20000>;
+			no-map;
+		};
+
+		aop_config_mem: memory@87f00000 {
+			reg = <0x0 0x87f00000 0x0 0x20000>;
+			no-map;
+		};
+
+		ipa_fw_mem: memory@87f20000 {
+			reg = <0x0 0x87f20000 0x0 0x10000>;
+			no-map;
+		};
+
+		secdata_mem: memory@87f30000 {
+			reg = <0x0 0x87f30000 0x0 0x1000>;
+			no-map;
+		};
+
+		tme_crashdump_mem: memory@87f31000 {
+			reg = <0x0 0x87f31000 0x0 0x40000>;
+			no-map;
+		};
+
+		tme_log_mem: memory@87f71000 {
+			reg = <0x0 0x87f71000 0x0 0x4000>;
+			no-map;
+		};
+
+		uefi_log_mem: memory@87f75000 {
+			reg = <0x0 0x87f75000 0x0 0x10000>;
+			no-map;
+		};
+
+		qdss_mem: memory@88800000 {
+			reg = <0x0 0x88800000 0x0 0x300000>;
+			no-map;
+		};
+
+		audio_heap_mem: memory@88b00000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0x88b00000 0x0 0x400000>;
+			no-map;
+		};
+
+		mpss_dsmharq_mem: memory@88f00000 {
+			reg = <0x0 0x88f00000 0x0 0x5080000>;
+			no-map;
+		};
+
+		q6_mpss_dtb_mem: memory@8df80000 {
+			reg = <0x0 0x8df80000 0x0 0x80000>;
+			no-map;
+		};
+
+		mpssadsp_mem: memory@8e000000 {
+			reg = <0x0 0x8e000000 0x0 0xf400000>;
+			no-map;
+		};
+
+		gunyah_trace_buffer_mem: memory@bdb00000 {
+			reg = <0x0 0xbdb00000 0x0 0x2000000>;
+			no-map;
+		};
+
+		smmu_debug_buf_mem: memory@bfb00000 {
+			reg = <0x0 0xbfb00000 0x0 0x100000>;
+			no-map;
+		};
+
+		hyp_smmu_s2_pt_mem: memory@bfc00000 {
+			reg = <0x0 0xbfc00000 0x0 0x400000>;
+			no-map;
+		};
+	};
+
+	smem: qcom,smem {
+		compatible = "qcom,smem";
+		memory-region = <&smem_mem>;
+		hwlocks = <&tcsr_mutex 3>;
+	};
+
+	soc: soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		compatible = "simple-bus";
+
+		tcsr_mutex: hwlock@1f40000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0x0 0x01f40000 0x0 0x40000>;
+			#hwlock-cells = <1>;
+		};
+
+		pdc: interrupt-controller@b220000 {
+			compatible = "qcom,sdx75-pdc", "qcom,pdc";
+			reg = <0x0 0xb220000 0x0 0x30000>,
+			      <0x0 0x174000f0 0x0 0x64>;
+			qcom,pdc-ranges = <0 147 52>,
+					  <52 266 32>,
+					  <84 500 59>;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupt-controller;
+		};
+
+		tlmm: pinctrl@f000000 {
+			compatible = "qcom,sdx75-tlmm";
+			reg = <0x0 0x0f000000 0x0 0x400000>;
+			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&tlmm 0 0 133>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			wakeup-parent = <&pdc>;
+		};
+
+		apps_smmu: iommu@15000000 {
+			compatible = "qcom,sdx75-smmu-500", "arm,mmu-500";
+			reg = <0x0 0x15000000 0x0 0x40000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <2>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		intc: interrupt-controller@17200000 {
+			compatible = "arm,gic-v3";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			#redistributor-regions = <1>;
+			redistributor-stride = <0x0 0x20000>;
+			reg = <0x0 0x17200000 0x0 0x10000>,
+			      <0x0 0x17260000 0x0 0x80000>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		timer@17420000 {
+			compatible = "arm,armv7-timer-mem";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			reg = <0x0 0x17420000 0x0 0x1000>;
+			clock-frequency = <19200000>;
+
+			frame@17421000 {
+				frame-number = <0>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0 0x17421000 0x0 0x1000>,
+				      <0x0 0x17422000 0x0 0x1000>;
+			};
+
+			frame@17423000 {
+				frame-number = <1>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0 0x17425000 0x0 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17425000 {
+				frame-number = <2>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0 0x17425000 0x0 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17427000 {
+				frame-number = <3>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0 0x17427000 0x0 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17429000 {
+				frame-number = <4>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0 0x17429000 0x0 0x1000>;
+				status = "disabled";
+			};
+
+			frame@1742b000 {
+				frame-number = <5>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0 0x1742b000 0x0 0x1000>;
+				status = "disabled";
+			};
+
+			frame@1742d000 {
+				frame-number = <6>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x0 0x1742d000 0x0 0x1000>;
+				status = "disabled";
+			};
+		};
+
+		apps_rsc: rsc@17a00000 {
+			label = "apps_rsc";
+			compatible = "qcom,rpmh-rsc";
+			reg = <0x0 0x17a00000 0x0 0x10000>,
+			      <0x0 0x17a10000 0x0 0x10000>,
+			      <0x0 0x17a20000 0x0 0x10000>;
+			reg-names = "drv-0", "drv-1", "drv-2";
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+
+			power-domains = <&CLUSTER_PD>;
+			qcom,tcs-offset = <0xd00>;
+			qcom,drv-id = <2>;
+			qcom,tcs-config = <ACTIVE_TCS    3>,
+					  <SLEEP_TCS     2>,
+					  <WAKE_TCS      2>,
+					  <CONTROL_TCS   0>;
+
+			apps_bcm_voter: bcm_voter {
+				compatible = "qcom,bcm-voter";
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <19200000>;
+	};
+};
-- 
2.7.4

From: Imran Shaik <quic_imrashai@quicinc.com>

Add support for GCC and RPMHCC clock nodes for SDX75 platform.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sdx75.dtsi | 37 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
index XXXXXXX..XXXXXXX 100644
--- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
@@ -XXX,XX +XXX,XX @@
  */
 
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sdx75-gcc.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
@@ -XXX,XX +XXX,XX @@
 		reg = <0 0 0 0>;
 	};
 
-	clocks { };
+	clocks {
+		xo_board: xo_board {
+			compatible = "fixed-clock";
+			clock-frequency = <76800000>;
+			clock-output-names = "xo_board";
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			clock-output-names = "sleep_clk";
+			#clock-cells = <0>;
+		};
+	};
 
 	cpus {
 		#address-cells = <2>;
@@ -XXX,XX +XXX,XX @@
 		ranges;
 		compatible = "simple-bus";
 
+		gcc: clock-controller@80000 {
+			compatible = "qcom,sdx75-gcc";
+			reg = <0x0 0x0080000 0x0 0x1f7400>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&sleep_clk>;
+			clock-names = "bi_tcxo",
+				      "sleep_clk";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
 		tcsr_mutex: hwlock@1f40000 {
 			compatible = "qcom,tcsr-mutex";
 			reg = <0x0 0x01f40000 0x0 0x40000>;
@@ -XXX,XX +XXX,XX @@
 			apps_bcm_voter: bcm_voter {
 				compatible = "qcom,bcm-voter";
 			};
+
+			rpmhcc: clock-controller {
+				compatible = "qcom,sdx75-rpmh-clk";
+				clocks = <&xo_board>;
+				clock-names = "xo";
+				#clock-cells = <1>;
+			};
+
 		};
 	};
 
-- 
2.7.4

Add the debug uart console node in devicetree.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sdx75.dtsi | 49 +++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
index XXXXXXX..XXXXXXX 100644
--- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
@@ -XXX,XX +XXX,XX @@
 			#power-domain-cells = <1>;
 		};
 
+		qupv3_id_0: geniqup@9c0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x0 0x009c0000 0x0 0x2000>;
+			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+			clock-names = "m-ahb",
+				      "s-ahb";
+			iommus = <&apps_smmu 0xe3 0x0>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			status = "disabled";
+
+			uart1: serial@984000 {
+				compatible = "qcom,geni-debug-uart";
+				reg = <0x0 0x00984000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+				interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qupv3_se1_2uart_tx_active>,
+					    <&qupv3_se1_2uart_rx_active>;
+				pinctrl-1 = <&qupv3_se1_2uart_sleep>;
+				pinctrl-names = "default",
+						"sleep";
+				status = "disabled";
+			};
+		};
+
 		tcsr_mutex: hwlock@1f40000 {
 			compatible = "qcom,tcsr-mutex";
 			reg = <0x0 0x01f40000 0x0 0x40000>;
@@ -XXX,XX +XXX,XX @@
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			wakeup-parent = <&pdc>;
+
+			qupv3_se1_2uart_tx_active: qupv3-se1-2uart-tx-active-state {
+				pins = "gpio12";
+				function = "qup_se1_l2_mira";
+				drive-strength= <2>;
+				bias-disable;
+			};
+
+			qupv3_se1_2uart_rx_active: qupv3-se1-2uart-rx-active-state {
+				pins = "gpio13";
+				function = "qup_se1_l3_mira";
+				drive-strength= <2>;
+				bias-disable;
+			};
+
+			qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state {
+				pins = "gpio12", "gpio13";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
 		};
 
 		apps_smmu: iommu@15000000 {
-- 
2.7.4

Hi,

Changes in v4:
 - Addressed some of the dt bindings check mentioned by Krzysztof.

Changes in v3:
 - Clubbed all the dt node into a single patch as suggested by Krzysztof.
 - Removed the applied patch.
 - Addressed some comments from Konrad and Dmitry.

Changes in v2:
 - Added the CPUFreq support patch.
 - Collected the Acked by tags.
 - Addressed some minor comments from Konrad.

With this current devicetree support, the IDP can boot into initramfsshell.

[1] https://lore.kernel.org/lkml/20230419133013.2563-3-quic_tdas@quicinc.com/
[2] https://lore.kernel.org/all/1684409015-25196-1-git-send-email-quic_rohiagar@quicinc.com/

Thanks,
Rohit.

Rohit Agarwal (5):
  dt-bindings: arm: qcom: Document SDX75 platform and boards
  dt-bindings: firmware: scm: Add compatible for SDX75
  dt-bindings: interrupt-controller: Add SDX75 PDC compatible
  dt-bindings: cpufreq: cpufreq-qcom-hw: Add SDX75 compatible
  arm64: dts: qcom: Add SDX75 platform and IDP board support

Documentation/devicetree/bindings/arm/qcom.yaml    |   7 +
 .../bindings/cpufreq/cpufreq-qcom-hw.yaml          |   1 +
 .../devicetree/bindings/firmware/qcom,scm.yaml     |   1 +
 .../bindings/interrupt-controller/qcom,pdc.yaml    |   1 +
 arch/arm64/boot/dts/qcom/Makefile                  |   1 +
 arch/arm64/boot/dts/qcom/sdx75-idp.dts             |  33 +
 arch/arm64/boot/dts/qcom/sdx75.dtsi                | 670 +++++++++++++++++++++
 7 files changed, 714 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sdx75-idp.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sdx75.dtsi

-- 
2.7.4

Document the SDX75 platform binding and also the boards using it.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 arch/arm64/boot/dts/qcom/Makefile      |   1 +
 arch/arm64/boot/dts/qcom/sdx75-idp.dts |  33 ++
 arch/arm64/boot/dts/qcom/sdx75.dtsi    | 670 +++++++++++++++++++++++++++++++++
 3 files changed, 704 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sdx75-idp.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sdx75.dtsi

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index XXXXXXX..XXXXXXX 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -XXX,XX +XXX,XX @@ dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-xiaomi-polaris.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-shift-axolotl.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm850-lenovo-yoga-c630.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm850-samsung-w737.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= sdx75-idp.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm4250-oneplus-billie2.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm6115p-lenovo-j606f.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm6125-sony-xperia-seine-pdx201.dtb
diff --git a/arch/arm64/boot/dts/qcom/sdx75-idp.dts b/arch/arm64/boot/dts/qcom/sdx75-idp.dts
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdx75-idp.dts
@@ -XXX,XX +XXX,XX @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "sdx75.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SDX75 IDP";
+	compatible = "qcom,sdx75-idp", "qcom,sdx75";
+
+	aliases {
+		serial0 = &uart1;
+	};
+};
+
+&chosen {
+	stdout-path = "serial0:115200n8";
+};
+
+&qupv3_id_0 {
+	status = "okay";
+};
+
+&tlmm {
+	gpio-reserved-ranges = <110 6>;
+};
+
+&uart1 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
@@ -XXX,XX +XXX,XX @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * SDX75 SoC device tree source
+ *
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ */
+
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sdx75-gcc.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&intc>;
+
+	chosen: chosen { };
+
+	clocks {
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			clock-frequency = <76800000>;
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			#clock-cells = <0>;
+		};
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x0>;
+			clocks = <&cpufreq_hw 0>;
+			enable-method = "psci";
+			power-domains = <&CPU_PD0>;
+			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			next-level-cache = <&L2_0>;
+
+			L2_0: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+				L3_0: l3-cache {
+					compatible = "cache";
+					cache-level = <3>;
+					cache-unified;
+				};
+			};
+		};
+
+		CPU1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x100>;
+			clocks = <&cpufreq_hw 0>;
+			enable-method = "psci";
+			power-domains = <&CPU_PD1>;
+			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			next-level-cache = <&L2_100>;
+
+			L2_100: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x200>;
+			clocks = <&cpufreq_hw 0>;
+			enable-method = "psci";
+			power-domains = <&CPU_PD2>;
+			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			next-level-cache = <&L2_200>;
+
+			L2_200: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x300>;
+			clocks = <&cpufreq_hw 0>;
+			enable-method = "psci";
+			power-domains = <&CPU_PD3>;
+			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			next-level-cache = <&L2_300>;
+
+			L2_300: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+
+				core2 {
+					cpu = <&CPU2>;
+				};
+
+				core3 {
+					cpu = <&CPU3>;
+				};
+			};
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			CPU_OFF: cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				entry-latency-us = <235>;
+				exit-latency-us = <428>;
+				min-residency-us = <1774>;
+				arm,psci-suspend-param = <0x40000003>;
+				local-timer-stop;
+			};
+
+			CPU_RAIL_OFF: cpu-rail-sleep-1 {
+				compatible = "arm,idle-state";
+				entry-latency-us = <800>;
+				exit-latency-us = <750>;
+				min-residency-us = <4090>;
+				arm,psci-suspend-param = <0x40000004>;
+				local-timer-stop;
+			};
+
+		};
+
+		domain-idle-states {
+			CLUSTER_SLEEP_0: cluster-sleep-0 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x41000044>;
+				entry-latency-us = <1050>;
+				exit-latency-us = <2500>;
+				min-residency-us = <5309>;
+			};
+
+			CLUSTER_SLEEP_1: cluster-sleep-1 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x41001344>;
+				entry-latency-us = <2761>;
+				exit-latency-us = <3964>;
+				min-residency-us = <8467>;
+			};
+
+			CLUSTER_SLEEP_2: cluster-sleep-2 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x4100b344>;
+				entry-latency-us = <2793>;
+				exit-latency-us = <4023>;
+				min-residency-us = <9826>;
+			};
+		};
+	};
+
+	firmware {
+		scm: scm {
+			compatible = "qcom,scm-sdx75", "qcom,scm";
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x0>;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+
+		CPU_PD0: power-domain-cpu0 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
+		};
+
+		CPU_PD1: power-domain-cpu1 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
+		};
+
+		CPU_PD2: power-domain-cpu2 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
+		};
+
+		CPU_PD3: power-domain-cpu3 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD>;
+			domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
+		};
+
+		CLUSTER_PD: power-domain-cpu-cluster0 {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>;
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		gunyah_hyp_mem: gunyah-hyp@80000000 {
+			reg = <0x0 0x80000000 0x0 0x800000>;
+			no-map;
+		};
+
+		hyp_elf_package_mem: hyp-elf-package@80800000 {
+			reg = <0x0 0x80800000 0x0 0x200000>;
+			no-map;
+		};
+
+		access_control_db_mem: access-control-db@81380000 {
+			reg = <0x0 0x81380000 0x0 0x80000>;
+			no-map;
+		};
+
+		qteetz_mem: qteetz@814e0000 {
+			reg = <0x0 0x814e0000 0x0 0x2a0000>;
+			no-map;
+		};
+
+		trusted_apps_mem: trusted-apps@81780000 {
+			reg = <0x0 0x81780000 0x0 0xa00000>;
+			no-map;
+		};
+
+		xbl_ramdump_mem: xbl-ramdump@87a00000 {
+			reg = <0x0 0x87a00000 0x0 0x1c0000>;
+			no-map;
+		};
+
+		cpucp_fw_mem: cpucp-fw@87c00000 {
+			reg = <0x0 0x87c00000 0x0 0x100000>;
+			no-map;
+		};
+
+		xbl_dtlog_mem: xbl-dtlog@87d00000 {
+			reg = <0x0 0x87d00000 0x0 0x40000>;
+			no-map;
+		};
+
+		xbl_sc_mem: xbl-sc@87d40000 {
+			reg = <0x0 0x87d40000 0x0 0x40000>;
+			no-map;
+		};
+
+		modem_efs_shared_mem: modem-efs-shared@87d80000 {
+			reg = <0x0 0x87d80000 0x0 0x10000>;
+			no-map;
+		};
+
+		aop_image_mem: aop-image@87e00000 {
+			reg = <0x0 0x87e00000 0x0 0x20000>;
+			no-map;
+		};
+
+		smem_mem: smem@87e20000 {
+			reg = <0x0 0x87e20000 0x0 0xc0000>;
+			no-map;
+		};
+
+		aop_cmd_db_mem: aop-cmd-db@87ee0000 {
+			compatible = "qcom,cmd-db";
+			reg = <0x0 0x87ee0000 0x0 0x20000>;
+			no-map;
+		};
+
+		aop_config_mem: aop-config@87f00000 {
+			reg = <0x0 0x87f00000 0x0 0x20000>;
+			no-map;
+		};
+
+		ipa_fw_mem: ipa-fw@87f20000 {
+			reg = <0x0 0x87f20000 0x0 0x10000>;
+			no-map;
+		};
+
+		secdata_mem: secdata@87f30000 {
+			reg = <0x0 0x87f30000 0x0 0x1000>;
+			no-map;
+		};
+
+		tme_crashdump_mem: tme-crashdump@87f31000 {
+			reg = <0x0 0x87f31000 0x0 0x40000>;
+			no-map;
+		};
+
+		tme_log_mem: tme-log@87f71000 {
+			reg = <0x0 0x87f71000 0x0 0x4000>;
+			no-map;
+		};
+
+		uefi_log_mem: uefi-log@87f75000 {
+			reg = <0x0 0x87f75000 0x0 0x10000>;
+			no-map;
+		};
+
+		qdss_mem: qdss@88800000 {
+			reg = <0x0 0x88800000 0x0 0x300000>;
+			no-map;
+		};
+
+		audio_heap_mem: audio-heap@88b00000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0x88b00000 0x0 0x400000>;
+			no-map;
+		};
+
+		mpss_dsmharq_mem: mpss-dsmharq@88f00000 {
+			reg = <0x0 0x88f00000 0x0 0x5080000>;
+			no-map;
+		};
+
+		q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 {
+			reg = <0x0 0x8df80000 0x0 0x80000>;
+			no-map;
+		};
+
+		mpssadsp_mem: mpssadsp@8e000000 {
+			reg = <0x0 0x8e000000 0x0 0xf400000>;
+			no-map;
+		};
+
+		gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 {
+			reg = <0x0 0xbdb00000 0x0 0x2000000>;
+			no-map;
+		};
+
+		smmu_debug_buf_mem: smmu-debug-buf@bfb00000 {
+			reg = <0x0 0xbfb00000 0x0 0x100000>;
+			no-map;
+		};
+
+		hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 {
+			reg = <0x0 0xbfc00000 0x0 0x400000>;
+			no-map;
+		};
+	};
+
+	smem: qcom,smem {
+		compatible = "qcom,smem";
+		memory-region = <&smem_mem>;
+		hwlocks = <&tcsr_mutex 3>;
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0 0 0 0 0x10 0>;
+		dma-ranges = <0 0 0 0 0x10 0>;
+
+		gcc: clock-controller@80000 {
+			compatible = "qcom,sdx75-gcc";
+			reg = <0x0 0x0080000 0x0 0x1f7400>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&sleep_clk>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		qupv3_id_0: geniqup@9c0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x0 0x009c0000 0x0 0x2000>;
+			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+			clock-names = "m-ahb",
+				      "s-ahb";
+			iommus = <&apps_smmu 0xe3 0x0>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			status = "disabled";
+
+			uart1: serial@984000 {
+				compatible = "qcom,geni-debug-uart";
+				reg = <0x0 0x00984000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qupv3_se1_2uart_active>;
+				pinctrl-1 = <&qupv3_se1_2uart_sleep>;
+				pinctrl-names = "default",
+						"sleep";
+				status = "disabled";
+			};
+		};
+
+		tcsr_mutex: hwlock@1f40000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0x0 0x01f40000 0x0 0x40000>;
+			#hwlock-cells = <1>;
+		};
+
+		pdc: interrupt-controller@b220000 {
+			compatible = "qcom,sdx75-pdc", "qcom,pdc";
+			reg = <0x0 0xb220000 0x0 0x30000>,
+			      <0x0 0x174000f0 0x0 0x64>;
+			qcom,pdc-ranges = <0 147 52>,
+					  <52 266 32>,
+					  <84 500 59>;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupt-controller;
+		};
+
+		tlmm: pinctrl@f000000 {
+			compatible = "qcom,sdx75-tlmm";
+			reg = <0x0 0x0f000000 0x0 0x400000>;
+			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&tlmm 0 0 133>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			wakeup-parent = <&pdc>;
+
+			qupv3_se1_2uart_active: qupv3-se1-2uart-active-state {
+				tx-pins {
+					pins = "gpio12";
+					function = "qup_se1_l2_mira";
+					drive-strength= <2>;
+					bias-disable;
+				};
+
+				rx-pins {
+					pins = "gpio13";
+					function = "qup_se1_l3_mira";
+					drive-strength= <2>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state {
+				pins = "gpio12", "gpio13";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		apps_smmu: iommu@15000000 {
+			compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x15000000 0x0 0x40000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <2>;
+			dma-coherent;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		intc: interrupt-controller@17200000 {
+			compatible = "arm,gic-v3";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			#redistributor-regions = <1>;
+			redistributor-stride = <0x0 0x20000>;
+			reg = <0x0 0x17200000 0x0 0x10000>,
+			      <0x0 0x17260000 0x0 0x80000>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		timer@17420000 {
+			compatible = "arm,armv7-timer-mem";
+			reg = <0x0 0x17420000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0 0 0x20000000>;
+
+			frame@17421000 {
+				reg = <0x17421000 0x1000>,
+				      <0x17422000 0x1000>;
+				frame-number = <0>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			frame@17423000 {
+				reg = <0x17423000 0x1000>;
+				frame-number = <1>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17425000 {
+				reg = <0x17425000 0x1000>;
+				frame-number = <2>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17427000 {
+				reg = <0x17427000 0x1000>;
+				frame-number = <3>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17429000 {
+				reg = <0x17429000 0x1000>;
+				frame-number = <4>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@1742b000 {
+				reg = <0x1742b000 0x1000>;
+				frame-number = <5>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@1742d000 {
+				reg = <0x1742d000 0x1000>;
+				frame-number = <6>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+
+		apps_rsc: rsc@17a00000 {
+			label = "apps_rsc";
+			compatible = "qcom,rpmh-rsc";
+			reg = <0x0 0x17a00000 0x0 0x10000>,
+			      <0x0 0x17a10000 0x0 0x10000>,
+			      <0x0 0x17a20000 0x0 0x10000>;
+			reg-names = "drv-0", "drv-1", "drv-2";
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+
+			power-domains = <&CLUSTER_PD>;
+			qcom,tcs-offset = <0xd00>;
+			qcom,drv-id = <2>;
+			qcom,tcs-config = <ACTIVE_TCS    3>,
+					  <SLEEP_TCS     2>,
+					  <WAKE_TCS      2>,
+					  <CONTROL_TCS   0>;
+
+			apps_bcm_voter: bcm-voter {
+				compatible = "qcom,bcm-voter";
+			};
+
+			rpmhcc: clock-controller {
+				compatible = "qcom,sdx75-rpmh-clk";
+				clocks = <&xo_board>;
+				clock-names = "xo";
+				#clock-cells = <1>;
+			};
+		};
+
+		cpufreq_hw: cpufreq@17d91000 {
+			compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss";
+			reg = <0x0 0x17d91000 0x0 0x1000>;
+			reg-names = "freq-domain0";
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GPLL0>;
+			clock-names = "xo",
+				      "alternate";
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "dcvsh-irq-0";
+			#freq-domain-cells = <1>;
+			#clock-cells = <1>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
-- 
2.7.4