Support for TEECR32_EL1 and TEEHBR32_EL1 was removed from binutils on the
basis that ThumbEE was removed from v8 before the spec was finalized (and
hence it never appeared in production silicon). Limit respective code to
Arm32 builds.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
Requires 5bbe1fe413f9 ("ARM: Drop ThumbEE support") to be reverted first.

Further cleanup up may be wanted, but I wasn't sure whether to fold this
into this patch: TEE{CR,HBR}32_EL1 are now unnecessary aliases, and the
32-bit-only TEE{CR,HBR} constants could be used instead.

Also cpu_has_thumbee may better be either hidden from Arm64, or be made
constant false there.

--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -111,13 +111,13 @@ static void ctxt_switch_from(struct vcpu
     p->arch.cntkctl = READ_SYSREG(CNTKCTL_EL1);
     virt_timer_save(p);
 
-    if ( is_32bit_domain(p->domain) && cpu_has_thumbee )
+#ifdef CONFIG_ARM_32
+    if ( cpu_has_thumbee )
     {
         p->arch.teecr = READ_SYSREG(TEECR32_EL1);
         p->arch.teehbr = READ_SYSREG(TEEHBR32_EL1);
     }
 
-#ifdef CONFIG_ARM_32
     p->arch.joscr = READ_CP32(JOSCR);
     p->arch.jmcr = READ_CP32(JMCR);
 #endif
@@ -244,13 +244,13 @@ static void ctxt_switch_to(struct vcpu *
     WRITE_SYSREG(n->arch.tpidrro_el0, TPIDRRO_EL0);
     WRITE_SYSREG(n->arch.tpidr_el1, TPIDR_EL1);
 
-    if ( is_32bit_domain(n->domain) && cpu_has_thumbee )
+#ifdef CONFIG_ARM_32
+    if ( cpu_has_thumbee )
     {
         WRITE_SYSREG(n->arch.teecr, TEECR32_EL1);
         WRITE_SYSREG(n->arch.teehbr, TEEHBR32_EL1);
     }
 
-#ifdef CONFIG_ARM_32
     WRITE_CP32(n->arch.joscr, JOSCR);
     WRITE_CP32(n->arch.jmcr, JMCR);
 #endif
--- a/xen/arch/arm/include/asm/domain.h
+++ b/xen/arch/arm/include/asm/domain.h
@@ -211,8 +211,9 @@ struct arch_vcpu
     register_t hcr_el2;
     register_t mdcr_el2;
 
-    uint32_t teecr, teehbr; /* ThumbEE, 32-bit guests only */
 #ifdef CONFIG_ARM_32
+    uint32_t teecr, teehbr; /* ThumbEE */
+
     /*
      * ARMv8 only supports a trivial implementation on Jazelle when in AArch32
      * mode and therefore has no extended control registers.