Most (if not all) Intel CPUs starting from Sandy Bridge have up to 8
event selectors per core, which could be halved per hyperthread.
However, current PV emulation logic doesn't support up to 8 event selector,
leading to errors when trying to access them, hence, preventing Linux from
driving the vPMU correctly.
Make sure up to MSR_P6_EVNTSEL(7) is usable, which is the same upper bound as
used in VMX code.
The check if the event selector actually exist for the hardware is done in
core2_vpmu_do_{rdmsr,wrmsr}, hence we're not allowing to access non-existent
MSRs.
Fixes: 27c554198666 ("x86/VPMU: add support for PMU register handling on PV guests")
Signed-off-by: Teddy Astie <teddy.astie@vates.tech>
---
xen/arch/x86/pv/emul-priv-op.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c
index 64d47ab677..b2556f9213 100644
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -990,7 +990,7 @@ static int cf_check read_msr(
return X86EMUL_OKAY;
case MSR_P6_PERFCTR(0) ... MSR_P6_PERFCTR(7):
- case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(3):
+ case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(7):
case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR2:
case MSR_CORE_PERF_FIXED_CTR_CTRL ... MSR_CORE_PERF_GLOBAL_OVF_CTRL:
if ( boot_cpu_data.vendor == X86_VENDOR_INTEL )
@@ -1167,7 +1167,7 @@ static int cf_check write_msr(
break;
case MSR_P6_PERFCTR(0) ... MSR_P6_PERFCTR(7):
- case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(3):
+ case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(7):
case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR2:
case MSR_CORE_PERF_FIXED_CTR_CTRL ... MSR_CORE_PERF_GLOBAL_OVF_CTRL:
if ( boot_cpu_data.vendor == X86_VENDOR_INTEL )
--
2.53.0
--
Teddy Astie | Vates XCP-ng Developer
XCP-ng & Xen Orchestra - Vates solutions
web: https://vates.tech