From: Andrei Semenov <andrei.semenov@vates.tech>

SYSCFG_MEM_ENCRYPT is the AMD SME MSR used to enable SME and AMD SEV.

Signed-off-by: Andrei Semenov <andrei.semenov@vates.tech>
---
 xen/arch/x86/include/asm/msr-index.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index 22d9e76e55..7620c4cd2e 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -221,6 +221,7 @@
 #define  SYSCFG_MTRR_VAR_DRAM_EN            (_AC(1, ULL) << 20)
 #define  SYSCFG_MTRR_TOM2_EN                (_AC(1, ULL) << 21)
 #define  SYSCFG_TOM2_FORCE_WB               (_AC(1, ULL) << 22)
+#define  SYSCFG_MEM_ENCRYPT                 (_AC(1, ULL) << 23)
 
 #define MSR_K8_IORR_BASE0                   _AC(0xc0010016, U)
 #define MSR_K8_IORR_MASK0                   _AC(0xc0010017, U)
-- 
2.49.0



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech

On 16.05.2025 11:31, Teddy Astie wrote:
> From: Andrei Semenov <andrei.semenov@vates.tech>
> 
> SYSCFG_MEM_ENCRYPT is the AMD SME MSR used to enable SME and AMD SEV.
> 
> Signed-off-by: Andrei Semenov <andrei.semenov@vates.tech>

Title and description talk of an entire MSR, yet then ...

> --- a/xen/arch/x86/include/asm/msr-index.h
> +++ b/xen/arch/x86/include/asm/msr-index.h
> @@ -221,6 +221,7 @@
>  #define  SYSCFG_MTRR_VAR_DRAM_EN            (_AC(1, ULL) << 20)
>  #define  SYSCFG_MTRR_TOM2_EN                (_AC(1, ULL) << 21)
>  #define  SYSCFG_TOM2_FORCE_WB               (_AC(1, ULL) << 22)
> +#define  SYSCFG_MEM_ENCRYPT                 (_AC(1, ULL) << 23)

... it's only a single bit. Such an addition is in principle okay to go
in at about any time, but content and description need to match.

Jan