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Xen Security Advisory CVE-2026-23554 / XSA-480
version 3
Use after free of paging structures in EPT
UPDATES IN VERSION 3
====================
Public release.
ISSUE DESCRIPTION
=================
The Intel EPT paging code uses an optimization to defer flushing of any cached
EPT state until the p2m lock is dropped, so that multiple modifications done
under the same locked region only issue a single flush.
Freeing of paging structures however is not deferred until the flushing is
done, and can result in freed pages transiently being present in cached state.
Such stale entries can point to memory ranges not owned by the guest, thus
allowing access to unintended memory regions.
IMPACT
======
Privilege escalation, Denial of Service (DoS) affecting the entire host,
and information leaks.
VULNERABLE SYSTEMS
==================
Xen 4.17 and onwards are vulnerable. Xen 4.16 and older are not vulnerable.
Only x86 Intel systems with EPT support are vulnerable.
Only x86 HVM/PVH guests using HAP can leverage the vulnerability on affected
systems.
MITIGATION
==========
There are no mitigations.
CREDITS
=======
This issue was discovered by Roger Pau Monné of XenServer.
RESOLUTION
==========
Applying the attached patch resolves this issue.
Note that patches for released versions are generally prepared to
apply to the stable branches, and may not apply cleanly to the most
recent release tarball. Downstreams are encouraged to update to the
tip of the stable branch before applying these patches.
xsa480.patch xen-unstable - Xen 4.17.x
$ sha256sum xsa480*
578f8fec3f34656e085419f6376d43987ffd6ed32e067b4024d3c83ce03a5901 xsa480.patch
$
DEPLOYMENT DURING EMBARGO
=========================
Deployment of the patches and/or mitigations described above (or
others which are substantially similar) is permitted during the
embargo, even on public-facing systems with untrusted guest users and
administrators.
But: Distribution of updated software is prohibited (except to other
members of the predisclosure list).
Predisclosure list members who wish to deploy significantly different
patches and/or mitigations, please contact the Xen Project Security
Team.
(Note: this during-embargo deployment notice is retained in
post-embargo publicly released Xen Project advisories, even though it
is then no longer applicable. This is to enable the community to have
oversight of the Xen Project Security Team's decisionmaking.)
For more information about permissible uses of embargoed information,
consult the Xen Project community's agreed Security Policy:
http://www.xenproject.org/security-policy.html
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From 45f6866e34b7e9ee8b6ac16d646a2e954c97e48e Mon Sep 17 00:00:00 2001
From: Roger Pau Monne <roger.pau@citrix.com>
Date: Tue, 17 Feb 2026 09:33:43 +0100
Subject: [PATCH] x86/p2m: issue a sync flush before freeing paging pages
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
In the EPT implementation, the defer flushing logic is used
unconditionally, and that would lead to paging memory being returned to the
paging pool before its references had been flushed.
Issue any pending flushes before freeing the paging memory back to the
pool.
Note AMD (NPT) and Shadow paging are not affected, as they don't implement
the deferred flushing logic.
This is XSA-480 / CVE-2026-23554
Fixes: 4a59e6bb3a96 ("x86/EPT: squash meaningless TLB flush")
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
---
xen/arch/x86/mm/p2m.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/xen/arch/x86/mm/p2m.c b/xen/arch/x86/mm/p2m.c
index e915da26a832..fddecdf978ec 100644
--- a/xen/arch/x86/mm/p2m.c
+++ b/xen/arch/x86/mm/p2m.c
@@ -479,6 +479,11 @@ void p2m_free_ptp(struct p2m_domain *p2m, struct page_info *pg)
ASSERT(p2m->domain);
ASSERT(p2m->domain->arch.paging.free_page);
+ /*
+ * Issue any pending flush here, in case it was deferred before. The page
+ * will be returned to the paging pool now.
+ */
+ p2m_tlb_flush_sync(p2m);
page_list_del(pg, &p2m->pages);
p2m->domain->arch.paging.free_page(p2m->domain, pg);
--
2.51.0
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