1: move PCI arrays next to the function using them 2: "com<N>=" command line options are x86-specific 3: drop stray "#ifdef CONFIG_HAS_PCI" Jan
Pure code motion; no functional change intended.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
v2: New.
--- a/xen/drivers/char/ns16550.c
+++ b/xen/drivers/char/ns16550.c
@@ -153,312 +153,6 @@ struct ns16550_config_param {
unsigned int uart_offset;
unsigned int first_offset;
};
-
-/*
- * Create lookup tables for specific devices. It is assumed that if
- * the device found is MMIO, then you have indexed it here. Else, the
- * driver does nothing for MMIO based devices.
- */
-static const struct ns16550_config_param __initconst uart_param[] = {
- [param_default] = {
- .reg_width = 1,
- .lsr_mask = UART_LSR_THRE,
- .max_ports = 1,
- },
- [param_trumanage] = {
- .reg_shift = 2,
- .reg_width = 1,
- .fifo_size = 16,
- .lsr_mask = (UART_LSR_THRE | UART_LSR_TEMT),
- .mmio = 1,
- .max_ports = 1,
- },
- [param_oxford] = {
- .base_baud = 4000000,
- .uart_offset = 0x200,
- .first_offset = 0x1000,
- .reg_width = 1,
- .fifo_size = 16,
- .lsr_mask = UART_LSR_THRE,
- .mmio = 1,
- .max_ports = 1, /* It can do more, but we would need more custom code.*/
- },
- [param_oxford_2port] = {
- .base_baud = 4000000,
- .uart_offset = 0x200,
- .first_offset = 0x1000,
- .reg_width = 1,
- .fifo_size = 16,
- .lsr_mask = UART_LSR_THRE,
- .mmio = 1,
- .max_ports = 2,
- },
- [param_pericom_1port] = {
- .base_baud = 921600,
- .uart_offset = 8,
- .reg_width = 1,
- .fifo_size = 16,
- .lsr_mask = UART_LSR_THRE,
- .bar0 = 1,
- .max_ports = 1,
- },
- [param_pericom_2port] = {
- .base_baud = 921600,
- .uart_offset = 8,
- .reg_width = 1,
- .fifo_size = 16,
- .lsr_mask = UART_LSR_THRE,
- .bar0 = 1,
- .max_ports = 2,
- },
- /*
- * Of the two following ones, we can't really use all of their ports,
- * unless ns16550_com[] would get grown.
- */
- [param_pericom_4port] = {
- .base_baud = 921600,
- .uart_offset = 8,
- .reg_width = 1,
- .fifo_size = 16,
- .lsr_mask = UART_LSR_THRE,
- .bar0 = 1,
- .max_ports = 4,
- },
- [param_pericom_8port] = {
- .base_baud = 921600,
- .uart_offset = 8,
- .reg_width = 1,
- .fifo_size = 16,
- .lsr_mask = UART_LSR_THRE,
- .bar0 = 1,
- .max_ports = 8,
- }
-};
-static const struct ns16550_config __initconst uart_config[] =
-{
- /* Broadcom TruManage device */
- {
- .vendor_id = PCI_VENDOR_ID_BROADCOM,
- .dev_id = 0x160a,
- .param = param_trumanage,
- },
- /* OXPCIe952 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc11b,
- .param = param_oxford,
- },
- /* OXPCIe952 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc11f,
- .param = param_oxford,
- },
- /* OXPCIe952 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc138,
- .param = param_oxford,
- },
- /* OXPCIe952 2 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc158,
- .param = param_oxford_2port,
- },
- /* OXPCIe952 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc13d,
- .param = param_oxford,
- },
- /* OXPCIe952 2 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc15d,
- .param = param_oxford_2port,
- },
- /* OXPCIe952 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc40b,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc40f,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc41b,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc41f,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc42b,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc42f,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc43b,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc43f,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc44b,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc44f,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc45b,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc45f,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc46b,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc46f,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc47b,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc47f,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc48b,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc48f,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc49b,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc49f,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc4ab,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc4af,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc4bb,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc4bf,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc4cb,
- .param = param_oxford,
- },
- /* OXPCIe200 1 Native UART */
- {
- .vendor_id = PCI_VENDOR_ID_OXSEMI,
- .dev_id = 0xc4cf,
- .param = param_oxford,
- },
- /* Pericom PI7C9X7951 Uno UART */
- {
- .vendor_id = PCI_VENDOR_ID_PERICOM,
- .dev_id = 0x7951,
- .param = param_pericom_1port
- },
- /* Pericom PI7C9X7952 Duo UART */
- {
- .vendor_id = PCI_VENDOR_ID_PERICOM,
- .dev_id = 0x7952,
- .param = param_pericom_2port
- },
- /* Pericom PI7C9X7954 Quad UART */
- {
- .vendor_id = PCI_VENDOR_ID_PERICOM,
- .dev_id = 0x7954,
- .param = param_pericom_4port
- },
- /* Pericom PI7C9X7958 Octal UART */
- {
- .vendor_id = PCI_VENDOR_ID_PERICOM,
- .dev_id = 0x7958,
- .param = param_pericom_8port
- }
-};
#endif
static void ns16550_delayed_resume(void *data);
@@ -1045,6 +739,314 @@ static int __init check_existence(struct
}
#ifdef CONFIG_HAS_PCI
+
+/*
+ * Create lookup tables for specific devices. It is assumed that if
+ * the device found is MMIO, then you have indexed it here. Else, the
+ * driver does nothing for MMIO based devices.
+ */
+static const struct ns16550_config_param __initconst uart_param[] = {
+ [param_default] = {
+ .reg_width = 1,
+ .lsr_mask = UART_LSR_THRE,
+ .max_ports = 1,
+ },
+ [param_trumanage] = {
+ .reg_shift = 2,
+ .reg_width = 1,
+ .fifo_size = 16,
+ .lsr_mask = (UART_LSR_THRE | UART_LSR_TEMT),
+ .mmio = 1,
+ .max_ports = 1,
+ },
+ [param_oxford] = {
+ .base_baud = 4000000,
+ .uart_offset = 0x200,
+ .first_offset = 0x1000,
+ .reg_width = 1,
+ .fifo_size = 16,
+ .lsr_mask = UART_LSR_THRE,
+ .mmio = 1,
+ .max_ports = 1, /* It can do more, but we would need more custom code.*/
+ },
+ [param_oxford_2port] = {
+ .base_baud = 4000000,
+ .uart_offset = 0x200,
+ .first_offset = 0x1000,
+ .reg_width = 1,
+ .fifo_size = 16,
+ .lsr_mask = UART_LSR_THRE,
+ .mmio = 1,
+ .max_ports = 2,
+ },
+ [param_pericom_1port] = {
+ .base_baud = 921600,
+ .uart_offset = 8,
+ .reg_width = 1,
+ .fifo_size = 16,
+ .lsr_mask = UART_LSR_THRE,
+ .bar0 = 1,
+ .max_ports = 1,
+ },
+ [param_pericom_2port] = {
+ .base_baud = 921600,
+ .uart_offset = 8,
+ .reg_width = 1,
+ .fifo_size = 16,
+ .lsr_mask = UART_LSR_THRE,
+ .bar0 = 1,
+ .max_ports = 2,
+ },
+ /*
+ * Of the two following ones, we can't really use all of their ports,
+ * unless ns16550_com[] would get grown.
+ */
+ [param_pericom_4port] = {
+ .base_baud = 921600,
+ .uart_offset = 8,
+ .reg_width = 1,
+ .fifo_size = 16,
+ .lsr_mask = UART_LSR_THRE,
+ .bar0 = 1,
+ .max_ports = 4,
+ },
+ [param_pericom_8port] = {
+ .base_baud = 921600,
+ .uart_offset = 8,
+ .reg_width = 1,
+ .fifo_size = 16,
+ .lsr_mask = UART_LSR_THRE,
+ .bar0 = 1,
+ .max_ports = 8,
+ }
+};
+
+static const struct ns16550_config __initconst uart_config[] =
+{
+ /* Broadcom TruManage device */
+ {
+ .vendor_id = PCI_VENDOR_ID_BROADCOM,
+ .dev_id = 0x160a,
+ .param = param_trumanage,
+ },
+ /* OXPCIe952 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc11b,
+ .param = param_oxford,
+ },
+ /* OXPCIe952 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc11f,
+ .param = param_oxford,
+ },
+ /* OXPCIe952 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc138,
+ .param = param_oxford,
+ },
+ /* OXPCIe952 2 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc158,
+ .param = param_oxford_2port,
+ },
+ /* OXPCIe952 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc13d,
+ .param = param_oxford,
+ },
+ /* OXPCIe952 2 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc15d,
+ .param = param_oxford_2port,
+ },
+ /* OXPCIe952 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc40b,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc40f,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc41b,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc41f,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc42b,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc42f,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc43b,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc43f,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc44b,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc44f,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc45b,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc45f,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc46b,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc46f,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc47b,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc47f,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc48b,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc48f,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc49b,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc49f,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc4ab,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc4af,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc4bb,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc4bf,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc4cb,
+ .param = param_oxford,
+ },
+ /* OXPCIe200 1 Native UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_OXSEMI,
+ .dev_id = 0xc4cf,
+ .param = param_oxford,
+ },
+ /* Pericom PI7C9X7951 Uno UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_PERICOM,
+ .dev_id = 0x7951,
+ .param = param_pericom_1port
+ },
+ /* Pericom PI7C9X7952 Duo UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_PERICOM,
+ .dev_id = 0x7952,
+ .param = param_pericom_2port
+ },
+ /* Pericom PI7C9X7954 Quad UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_PERICOM,
+ .dev_id = 0x7954,
+ .param = param_pericom_4port
+ },
+ /* Pericom PI7C9X7958 Octal UART */
+ {
+ .vendor_id = PCI_VENDOR_ID_PERICOM,
+ .dev_id = 0x7958,
+ .param = param_pericom_8port
+ }
+};
+
static int __init
pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx)
{
@@ -1211,7 +1213,8 @@ pci_uart_config(struct ns16550 *uart, bo
return 0;
}
-#endif
+
+#endif /* CONFIG_HAS_PCI */
/*
* Used to parse name value pairs and return which value it is along with
On Mon, 23 Nov 2020, Jan Beulich wrote:
> Pure code motion; no functional change intended.
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
> ---
> v2: New.
>
> --- a/xen/drivers/char/ns16550.c
> +++ b/xen/drivers/char/ns16550.c
> @@ -153,312 +153,6 @@ struct ns16550_config_param {
> unsigned int uart_offset;
> unsigned int first_offset;
> };
> -
> -/*
> - * Create lookup tables for specific devices. It is assumed that if
> - * the device found is MMIO, then you have indexed it here. Else, the
> - * driver does nothing for MMIO based devices.
> - */
> -static const struct ns16550_config_param __initconst uart_param[] = {
> - [param_default] = {
> - .reg_width = 1,
> - .lsr_mask = UART_LSR_THRE,
> - .max_ports = 1,
> - },
> - [param_trumanage] = {
> - .reg_shift = 2,
> - .reg_width = 1,
> - .fifo_size = 16,
> - .lsr_mask = (UART_LSR_THRE | UART_LSR_TEMT),
> - .mmio = 1,
> - .max_ports = 1,
> - },
> - [param_oxford] = {
> - .base_baud = 4000000,
> - .uart_offset = 0x200,
> - .first_offset = 0x1000,
> - .reg_width = 1,
> - .fifo_size = 16,
> - .lsr_mask = UART_LSR_THRE,
> - .mmio = 1,
> - .max_ports = 1, /* It can do more, but we would need more custom code.*/
> - },
> - [param_oxford_2port] = {
> - .base_baud = 4000000,
> - .uart_offset = 0x200,
> - .first_offset = 0x1000,
> - .reg_width = 1,
> - .fifo_size = 16,
> - .lsr_mask = UART_LSR_THRE,
> - .mmio = 1,
> - .max_ports = 2,
> - },
> - [param_pericom_1port] = {
> - .base_baud = 921600,
> - .uart_offset = 8,
> - .reg_width = 1,
> - .fifo_size = 16,
> - .lsr_mask = UART_LSR_THRE,
> - .bar0 = 1,
> - .max_ports = 1,
> - },
> - [param_pericom_2port] = {
> - .base_baud = 921600,
> - .uart_offset = 8,
> - .reg_width = 1,
> - .fifo_size = 16,
> - .lsr_mask = UART_LSR_THRE,
> - .bar0 = 1,
> - .max_ports = 2,
> - },
> - /*
> - * Of the two following ones, we can't really use all of their ports,
> - * unless ns16550_com[] would get grown.
> - */
> - [param_pericom_4port] = {
> - .base_baud = 921600,
> - .uart_offset = 8,
> - .reg_width = 1,
> - .fifo_size = 16,
> - .lsr_mask = UART_LSR_THRE,
> - .bar0 = 1,
> - .max_ports = 4,
> - },
> - [param_pericom_8port] = {
> - .base_baud = 921600,
> - .uart_offset = 8,
> - .reg_width = 1,
> - .fifo_size = 16,
> - .lsr_mask = UART_LSR_THRE,
> - .bar0 = 1,
> - .max_ports = 8,
> - }
> -};
> -static const struct ns16550_config __initconst uart_config[] =
> -{
> - /* Broadcom TruManage device */
> - {
> - .vendor_id = PCI_VENDOR_ID_BROADCOM,
> - .dev_id = 0x160a,
> - .param = param_trumanage,
> - },
> - /* OXPCIe952 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc11b,
> - .param = param_oxford,
> - },
> - /* OXPCIe952 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc11f,
> - .param = param_oxford,
> - },
> - /* OXPCIe952 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc138,
> - .param = param_oxford,
> - },
> - /* OXPCIe952 2 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc158,
> - .param = param_oxford_2port,
> - },
> - /* OXPCIe952 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc13d,
> - .param = param_oxford,
> - },
> - /* OXPCIe952 2 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc15d,
> - .param = param_oxford_2port,
> - },
> - /* OXPCIe952 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc40b,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc40f,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc41b,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc41f,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc42b,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc42f,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc43b,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc43f,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc44b,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc44f,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc45b,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc45f,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc46b,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc46f,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc47b,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc47f,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc48b,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc48f,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc49b,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc49f,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc4ab,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc4af,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc4bb,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc4bf,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc4cb,
> - .param = param_oxford,
> - },
> - /* OXPCIe200 1 Native UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
> - .dev_id = 0xc4cf,
> - .param = param_oxford,
> - },
> - /* Pericom PI7C9X7951 Uno UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_PERICOM,
> - .dev_id = 0x7951,
> - .param = param_pericom_1port
> - },
> - /* Pericom PI7C9X7952 Duo UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_PERICOM,
> - .dev_id = 0x7952,
> - .param = param_pericom_2port
> - },
> - /* Pericom PI7C9X7954 Quad UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_PERICOM,
> - .dev_id = 0x7954,
> - .param = param_pericom_4port
> - },
> - /* Pericom PI7C9X7958 Octal UART */
> - {
> - .vendor_id = PCI_VENDOR_ID_PERICOM,
> - .dev_id = 0x7958,
> - .param = param_pericom_8port
> - }
> -};
> #endif
>
> static void ns16550_delayed_resume(void *data);
> @@ -1045,6 +739,314 @@ static int __init check_existence(struct
> }
>
> #ifdef CONFIG_HAS_PCI
> +
> +/*
> + * Create lookup tables for specific devices. It is assumed that if
> + * the device found is MMIO, then you have indexed it here. Else, the
> + * driver does nothing for MMIO based devices.
> + */
> +static const struct ns16550_config_param __initconst uart_param[] = {
> + [param_default] = {
> + .reg_width = 1,
> + .lsr_mask = UART_LSR_THRE,
> + .max_ports = 1,
> + },
> + [param_trumanage] = {
> + .reg_shift = 2,
> + .reg_width = 1,
> + .fifo_size = 16,
> + .lsr_mask = (UART_LSR_THRE | UART_LSR_TEMT),
> + .mmio = 1,
> + .max_ports = 1,
> + },
> + [param_oxford] = {
> + .base_baud = 4000000,
> + .uart_offset = 0x200,
> + .first_offset = 0x1000,
> + .reg_width = 1,
> + .fifo_size = 16,
> + .lsr_mask = UART_LSR_THRE,
> + .mmio = 1,
> + .max_ports = 1, /* It can do more, but we would need more custom code.*/
> + },
> + [param_oxford_2port] = {
> + .base_baud = 4000000,
> + .uart_offset = 0x200,
> + .first_offset = 0x1000,
> + .reg_width = 1,
> + .fifo_size = 16,
> + .lsr_mask = UART_LSR_THRE,
> + .mmio = 1,
> + .max_ports = 2,
> + },
> + [param_pericom_1port] = {
> + .base_baud = 921600,
> + .uart_offset = 8,
> + .reg_width = 1,
> + .fifo_size = 16,
> + .lsr_mask = UART_LSR_THRE,
> + .bar0 = 1,
> + .max_ports = 1,
> + },
> + [param_pericom_2port] = {
> + .base_baud = 921600,
> + .uart_offset = 8,
> + .reg_width = 1,
> + .fifo_size = 16,
> + .lsr_mask = UART_LSR_THRE,
> + .bar0 = 1,
> + .max_ports = 2,
> + },
> + /*
> + * Of the two following ones, we can't really use all of their ports,
> + * unless ns16550_com[] would get grown.
> + */
> + [param_pericom_4port] = {
> + .base_baud = 921600,
> + .uart_offset = 8,
> + .reg_width = 1,
> + .fifo_size = 16,
> + .lsr_mask = UART_LSR_THRE,
> + .bar0 = 1,
> + .max_ports = 4,
> + },
> + [param_pericom_8port] = {
> + .base_baud = 921600,
> + .uart_offset = 8,
> + .reg_width = 1,
> + .fifo_size = 16,
> + .lsr_mask = UART_LSR_THRE,
> + .bar0 = 1,
> + .max_ports = 8,
> + }
> +};
> +
> +static const struct ns16550_config __initconst uart_config[] =
> +{
> + /* Broadcom TruManage device */
> + {
> + .vendor_id = PCI_VENDOR_ID_BROADCOM,
> + .dev_id = 0x160a,
> + .param = param_trumanage,
> + },
> + /* OXPCIe952 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc11b,
> + .param = param_oxford,
> + },
> + /* OXPCIe952 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc11f,
> + .param = param_oxford,
> + },
> + /* OXPCIe952 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc138,
> + .param = param_oxford,
> + },
> + /* OXPCIe952 2 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc158,
> + .param = param_oxford_2port,
> + },
> + /* OXPCIe952 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc13d,
> + .param = param_oxford,
> + },
> + /* OXPCIe952 2 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc15d,
> + .param = param_oxford_2port,
> + },
> + /* OXPCIe952 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc40b,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc40f,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc41b,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc41f,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc42b,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc42f,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc43b,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc43f,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc44b,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc44f,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc45b,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc45f,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc46b,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc46f,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc47b,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc47f,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc48b,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc48f,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc49b,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc49f,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc4ab,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc4af,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc4bb,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc4bf,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc4cb,
> + .param = param_oxford,
> + },
> + /* OXPCIe200 1 Native UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
> + .dev_id = 0xc4cf,
> + .param = param_oxford,
> + },
> + /* Pericom PI7C9X7951 Uno UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_PERICOM,
> + .dev_id = 0x7951,
> + .param = param_pericom_1port
> + },
> + /* Pericom PI7C9X7952 Duo UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_PERICOM,
> + .dev_id = 0x7952,
> + .param = param_pericom_2port
> + },
> + /* Pericom PI7C9X7954 Quad UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_PERICOM,
> + .dev_id = 0x7954,
> + .param = param_pericom_4port
> + },
> + /* Pericom PI7C9X7958 Octal UART */
> + {
> + .vendor_id = PCI_VENDOR_ID_PERICOM,
> + .dev_id = 0x7958,
> + .param = param_pericom_8port
> + }
> +};
> +
> static int __init
> pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx)
> {
> @@ -1211,7 +1213,8 @@ pci_uart_config(struct ns16550 *uart, bo
>
> return 0;
> }
> -#endif
> +
> +#endif /* CONFIG_HAS_PCI */
>
> /*
> * Used to parse name value pairs and return which value it is along with
>
Hello ,
> On 24 Nov 2020, at 12:02 am, Stefano Stabellini <sstabellini@kernel.org> wrote:
>
> On Mon, 23 Nov 2020, Jan Beulich wrote:
>> Pure code motion; no functional change intended.
>>
>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>
> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
>
Reviewed-by: Rahul Singh <rahul.singh@arm.com>
Regards,
Rahul
>
>> ---
>> v2: New.
>>
>> --- a/xen/drivers/char/ns16550.c
>> +++ b/xen/drivers/char/ns16550.c
>> @@ -153,312 +153,6 @@ struct ns16550_config_param {
>> unsigned int uart_offset;
>> unsigned int first_offset;
>> };
>> -
>> -/*
>> - * Create lookup tables for specific devices. It is assumed that if
>> - * the device found is MMIO, then you have indexed it here. Else, the
>> - * driver does nothing for MMIO based devices.
>> - */
>> -static const struct ns16550_config_param __initconst uart_param[] = {
>> - [param_default] = {
>> - .reg_width = 1,
>> - .lsr_mask = UART_LSR_THRE,
>> - .max_ports = 1,
>> - },
>> - [param_trumanage] = {
>> - .reg_shift = 2,
>> - .reg_width = 1,
>> - .fifo_size = 16,
>> - .lsr_mask = (UART_LSR_THRE | UART_LSR_TEMT),
>> - .mmio = 1,
>> - .max_ports = 1,
>> - },
>> - [param_oxford] = {
>> - .base_baud = 4000000,
>> - .uart_offset = 0x200,
>> - .first_offset = 0x1000,
>> - .reg_width = 1,
>> - .fifo_size = 16,
>> - .lsr_mask = UART_LSR_THRE,
>> - .mmio = 1,
>> - .max_ports = 1, /* It can do more, but we would need more custom code.*/
>> - },
>> - [param_oxford_2port] = {
>> - .base_baud = 4000000,
>> - .uart_offset = 0x200,
>> - .first_offset = 0x1000,
>> - .reg_width = 1,
>> - .fifo_size = 16,
>> - .lsr_mask = UART_LSR_THRE,
>> - .mmio = 1,
>> - .max_ports = 2,
>> - },
>> - [param_pericom_1port] = {
>> - .base_baud = 921600,
>> - .uart_offset = 8,
>> - .reg_width = 1,
>> - .fifo_size = 16,
>> - .lsr_mask = UART_LSR_THRE,
>> - .bar0 = 1,
>> - .max_ports = 1,
>> - },
>> - [param_pericom_2port] = {
>> - .base_baud = 921600,
>> - .uart_offset = 8,
>> - .reg_width = 1,
>> - .fifo_size = 16,
>> - .lsr_mask = UART_LSR_THRE,
>> - .bar0 = 1,
>> - .max_ports = 2,
>> - },
>> - /*
>> - * Of the two following ones, we can't really use all of their ports,
>> - * unless ns16550_com[] would get grown.
>> - */
>> - [param_pericom_4port] = {
>> - .base_baud = 921600,
>> - .uart_offset = 8,
>> - .reg_width = 1,
>> - .fifo_size = 16,
>> - .lsr_mask = UART_LSR_THRE,
>> - .bar0 = 1,
>> - .max_ports = 4,
>> - },
>> - [param_pericom_8port] = {
>> - .base_baud = 921600,
>> - .uart_offset = 8,
>> - .reg_width = 1,
>> - .fifo_size = 16,
>> - .lsr_mask = UART_LSR_THRE,
>> - .bar0 = 1,
>> - .max_ports = 8,
>> - }
>> -};
>> -static const struct ns16550_config __initconst uart_config[] =
>> -{
>> - /* Broadcom TruManage device */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_BROADCOM,
>> - .dev_id = 0x160a,
>> - .param = param_trumanage,
>> - },
>> - /* OXPCIe952 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc11b,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe952 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc11f,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe952 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc138,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe952 2 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc158,
>> - .param = param_oxford_2port,
>> - },
>> - /* OXPCIe952 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc13d,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe952 2 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc15d,
>> - .param = param_oxford_2port,
>> - },
>> - /* OXPCIe952 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc40b,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc40f,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc41b,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc41f,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc42b,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc42f,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc43b,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc43f,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc44b,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc44f,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc45b,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc45f,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc46b,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc46f,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc47b,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc47f,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc48b,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc48f,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc49b,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc49f,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc4ab,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc4af,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc4bb,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc4bf,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc4cb,
>> - .param = param_oxford,
>> - },
>> - /* OXPCIe200 1 Native UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> - .dev_id = 0xc4cf,
>> - .param = param_oxford,
>> - },
>> - /* Pericom PI7C9X7951 Uno UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_PERICOM,
>> - .dev_id = 0x7951,
>> - .param = param_pericom_1port
>> - },
>> - /* Pericom PI7C9X7952 Duo UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_PERICOM,
>> - .dev_id = 0x7952,
>> - .param = param_pericom_2port
>> - },
>> - /* Pericom PI7C9X7954 Quad UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_PERICOM,
>> - .dev_id = 0x7954,
>> - .param = param_pericom_4port
>> - },
>> - /* Pericom PI7C9X7958 Octal UART */
>> - {
>> - .vendor_id = PCI_VENDOR_ID_PERICOM,
>> - .dev_id = 0x7958,
>> - .param = param_pericom_8port
>> - }
>> -};
>> #endif
>>
>> static void ns16550_delayed_resume(void *data);
>> @@ -1045,6 +739,314 @@ static int __init check_existence(struct
>> }
>>
>> #ifdef CONFIG_HAS_PCI
>> +
>> +/*
>> + * Create lookup tables for specific devices. It is assumed that if
>> + * the device found is MMIO, then you have indexed it here. Else, the
>> + * driver does nothing for MMIO based devices.
>> + */
>> +static const struct ns16550_config_param __initconst uart_param[] = {
>> + [param_default] = {
>> + .reg_width = 1,
>> + .lsr_mask = UART_LSR_THRE,
>> + .max_ports = 1,
>> + },
>> + [param_trumanage] = {
>> + .reg_shift = 2,
>> + .reg_width = 1,
>> + .fifo_size = 16,
>> + .lsr_mask = (UART_LSR_THRE | UART_LSR_TEMT),
>> + .mmio = 1,
>> + .max_ports = 1,
>> + },
>> + [param_oxford] = {
>> + .base_baud = 4000000,
>> + .uart_offset = 0x200,
>> + .first_offset = 0x1000,
>> + .reg_width = 1,
>> + .fifo_size = 16,
>> + .lsr_mask = UART_LSR_THRE,
>> + .mmio = 1,
>> + .max_ports = 1, /* It can do more, but we would need more custom code.*/
>> + },
>> + [param_oxford_2port] = {
>> + .base_baud = 4000000,
>> + .uart_offset = 0x200,
>> + .first_offset = 0x1000,
>> + .reg_width = 1,
>> + .fifo_size = 16,
>> + .lsr_mask = UART_LSR_THRE,
>> + .mmio = 1,
>> + .max_ports = 2,
>> + },
>> + [param_pericom_1port] = {
>> + .base_baud = 921600,
>> + .uart_offset = 8,
>> + .reg_width = 1,
>> + .fifo_size = 16,
>> + .lsr_mask = UART_LSR_THRE,
>> + .bar0 = 1,
>> + .max_ports = 1,
>> + },
>> + [param_pericom_2port] = {
>> + .base_baud = 921600,
>> + .uart_offset = 8,
>> + .reg_width = 1,
>> + .fifo_size = 16,
>> + .lsr_mask = UART_LSR_THRE,
>> + .bar0 = 1,
>> + .max_ports = 2,
>> + },
>> + /*
>> + * Of the two following ones, we can't really use all of their ports,
>> + * unless ns16550_com[] would get grown.
>> + */
>> + [param_pericom_4port] = {
>> + .base_baud = 921600,
>> + .uart_offset = 8,
>> + .reg_width = 1,
>> + .fifo_size = 16,
>> + .lsr_mask = UART_LSR_THRE,
>> + .bar0 = 1,
>> + .max_ports = 4,
>> + },
>> + [param_pericom_8port] = {
>> + .base_baud = 921600,
>> + .uart_offset = 8,
>> + .reg_width = 1,
>> + .fifo_size = 16,
>> + .lsr_mask = UART_LSR_THRE,
>> + .bar0 = 1,
>> + .max_ports = 8,
>> + }
>> +};
>> +
>> +static const struct ns16550_config __initconst uart_config[] =
>> +{
>> + /* Broadcom TruManage device */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_BROADCOM,
>> + .dev_id = 0x160a,
>> + .param = param_trumanage,
>> + },
>> + /* OXPCIe952 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc11b,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe952 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc11f,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe952 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc138,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe952 2 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc158,
>> + .param = param_oxford_2port,
>> + },
>> + /* OXPCIe952 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc13d,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe952 2 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc15d,
>> + .param = param_oxford_2port,
>> + },
>> + /* OXPCIe952 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc40b,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc40f,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc41b,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc41f,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc42b,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc42f,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc43b,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc43f,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc44b,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc44f,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc45b,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc45f,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc46b,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc46f,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc47b,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc47f,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc48b,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc48f,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc49b,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc49f,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc4ab,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc4af,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc4bb,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc4bf,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc4cb,
>> + .param = param_oxford,
>> + },
>> + /* OXPCIe200 1 Native UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_OXSEMI,
>> + .dev_id = 0xc4cf,
>> + .param = param_oxford,
>> + },
>> + /* Pericom PI7C9X7951 Uno UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_PERICOM,
>> + .dev_id = 0x7951,
>> + .param = param_pericom_1port
>> + },
>> + /* Pericom PI7C9X7952 Duo UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_PERICOM,
>> + .dev_id = 0x7952,
>> + .param = param_pericom_2port
>> + },
>> + /* Pericom PI7C9X7954 Quad UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_PERICOM,
>> + .dev_id = 0x7954,
>> + .param = param_pericom_4port
>> + },
>> + /* Pericom PI7C9X7958 Octal UART */
>> + {
>> + .vendor_id = PCI_VENDOR_ID_PERICOM,
>> + .dev_id = 0x7958,
>> + .param = param_pericom_8port
>> + }
>> +};
>> +
>> static int __init
>> pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx)
>> {
>> @@ -1211,7 +1213,8 @@ pci_uart_config(struct ns16550 *uart, bo
>>
>> return 0;
>> }
>> -#endif
>> +
>> +#endif /* CONFIG_HAS_PCI */
>>
>> /*
>> * Used to parse name value pairs and return which value it is along with
>>
Pure code motion (plus the addition of "#ifdef CONFIG_X86); no
functional change intended.
Reported-by: Julien Grall <julien@xen.org>
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
v2: Re-base over new earlier patch.
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -318,8 +318,8 @@ Interrupts. Specifying zero disables CM
Flag to indicate whether to probe for a CMOS Real Time Clock irrespective of
ACPI indicating none to be there.
-### com1
-### com2
+### com1 (x86)
+### com2 (x86)
> `= <baud>[/<base-baud>][,[DPS][,[<io-base>|pci|amt][,[<irq>|msi][,[<port-bdf>][,[<bridge-bdf>]]]]]]`
Both option `com1` and `com2` follow the same format.
--- a/xen/drivers/char/ns16550.c
+++ b/xen/drivers/char/ns16550.c
@@ -31,38 +31,6 @@
#include <asm/fixmap.h>
#endif
-/*
- * Configure serial port with a string:
- * <baud>[/<base_baud>][,DPS[,<io-base>[,<irq>[,<port-bdf>[,<bridge-bdf>]]]]].
- * The tail of the string can be omitted if platform defaults are sufficient.
- * If the baud rate is pre-configured, perhaps by a bootloader, then 'auto'
- * can be specified in place of a numeric baud rate. Polled mode is specified
- * by requesting irq 0.
- */
-static char __initdata opt_com1[128] = "";
-static char __initdata opt_com2[128] = "";
-string_param("com1", opt_com1);
-string_param("com2", opt_com2);
-
-enum serial_param_type {
- baud,
- clock_hz,
- data_bits,
- io_base,
- irq,
- parity,
- reg_shift,
- reg_width,
- stop_bits,
-#ifdef CONFIG_HAS_PCI
- bridge_bdf,
- device,
- port_bdf,
-#endif
- /* List all parameters before this line. */
- num_serial_params
-};
-
static struct ns16550 {
int baud, clock_hz, data_bits, parity, stop_bits, fifo_size, irq;
u64 io_base; /* I/O port or memory-mapped I/O address. */
@@ -98,32 +66,6 @@ static struct ns16550 {
#endif
} ns16550_com[2] = { { 0 } };
-struct serial_param_var {
- char name[12];
- enum serial_param_type type;
-};
-
-/*
- * Enum struct keeping a table of all accepted parameter names for parsing
- * com_console_options for serial port com1 and com2.
- */
-static const struct serial_param_var __initconst sp_vars[] = {
- {"baud", baud},
- {"clock-hz", clock_hz},
- {"data-bits", data_bits},
- {"io-base", io_base},
- {"irq", irq},
- {"parity", parity},
- {"reg-shift", reg_shift},
- {"reg-width", reg_width},
- {"stop-bits", stop_bits},
-#ifdef CONFIG_HAS_PCI
- {"bridge", bridge_bdf},
- {"dev", device},
- {"port", port_bdf},
-#endif
-};
-
#ifdef CONFIG_HAS_PCI
struct ns16550_config {
u16 vendor_id;
@@ -674,6 +616,19 @@ static struct uart_driver __read_mostly
#endif
};
+static void ns16550_init_common(struct ns16550 *uart)
+{
+ uart->clock_hz = UART_CLOCK_HZ;
+
+ /* Default is no transmit FIFO. */
+ uart->fifo_size = 1;
+
+ /* Default lsr_mask = UART_LSR_THRE */
+ uart->lsr_mask = UART_LSR_THRE;
+}
+
+#ifdef CONFIG_X86
+
static int __init parse_parity_char(int c)
{
switch ( c )
@@ -1217,6 +1172,64 @@ pci_uart_config(struct ns16550 *uart, bo
#endif /* CONFIG_HAS_PCI */
/*
+ * Configure serial port with a string:
+ * <baud>[/<base_baud>][,DPS[,<io-base>[,<irq>[,<port-bdf>[,<bridge-bdf>]]]]].
+ * The tail of the string can be omitted if platform defaults are sufficient.
+ * If the baud rate is pre-configured, perhaps by a bootloader, then 'auto'
+ * can be specified in place of a numeric baud rate. Polled mode is specified
+ * by requesting irq 0.
+ */
+static char __initdata opt_com1[128] = "";
+static char __initdata opt_com2[128] = "";
+string_param("com1", opt_com1);
+string_param("com2", opt_com2);
+
+enum serial_param_type {
+ baud,
+ clock_hz,
+ data_bits,
+ io_base,
+ irq,
+ parity,
+ reg_shift,
+ reg_width,
+ stop_bits,
+#ifdef CONFIG_HAS_PCI
+ bridge_bdf,
+ device,
+ port_bdf,
+#endif
+ /* List all parameters before this line. */
+ num_serial_params
+};
+
+struct serial_param_var {
+ char name[12];
+ enum serial_param_type type;
+};
+
+/*
+ * Enum struct keeping a table of all accepted parameter names for parsing
+ * com_console_options for serial port com1 and com2.
+ */
+static const struct serial_param_var __initconst sp_vars[] = {
+ {"baud", baud},
+ {"clock-hz", clock_hz},
+ {"data-bits", data_bits},
+ {"io-base", io_base},
+ {"irq", irq},
+ {"parity", parity},
+ {"reg-shift", reg_shift},
+ {"reg-width", reg_width},
+ {"stop-bits", stop_bits},
+#ifdef CONFIG_HAS_PCI
+ {"bridge", bridge_bdf},
+ {"dev", device},
+ {"port", port_bdf},
+#endif
+};
+
+/*
* Used to parse name value pairs and return which value it is along with
* pointer for the extracted value.
*/
@@ -1504,17 +1517,6 @@ static void __init ns16550_parse_port_co
serial_register_uart(uart - ns16550_com, &ns16550_driver, uart);
}
-static void ns16550_init_common(struct ns16550 *uart)
-{
- uart->clock_hz = UART_CLOCK_HZ;
-
- /* Default is no transmit FIFO. */
- uart->fifo_size = 1;
-
- /* Default lsr_mask = UART_LSR_THRE */
- uart->lsr_mask = UART_LSR_THRE;
-}
-
void __init ns16550_init(int index, struct ns16550_defaults *defaults)
{
struct ns16550 *uart;
@@ -1541,6 +1543,8 @@ void __init ns16550_init(int index, stru
ns16550_parse_port_config(uart, (index == 0) ? opt_com1 : opt_com2);
}
+#endif /* CONFIG_X86 */
+
#ifdef CONFIG_HAS_DEVICE_TREE
static int __init ns16550_uart_dt_init(struct dt_device_node *dev,
const void *data)
On Mon, 23 Nov 2020, Jan Beulich wrote:
> Pure code motion (plus the addition of "#ifdef CONFIG_X86); no
> functional change intended.
>
> Reported-by: Julien Grall <julien@xen.org>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
Great cleanup
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
> ---
> v2: Re-base over new earlier patch.
>
> --- a/docs/misc/xen-command-line.pandoc
> +++ b/docs/misc/xen-command-line.pandoc
> @@ -318,8 +318,8 @@ Interrupts. Specifying zero disables CM
> Flag to indicate whether to probe for a CMOS Real Time Clock irrespective of
> ACPI indicating none to be there.
>
> -### com1
> -### com2
> +### com1 (x86)
> +### com2 (x86)
> > `= <baud>[/<base-baud>][,[DPS][,[<io-base>|pci|amt][,[<irq>|msi][,[<port-bdf>][,[<bridge-bdf>]]]]]]`
>
> Both option `com1` and `com2` follow the same format.
> --- a/xen/drivers/char/ns16550.c
> +++ b/xen/drivers/char/ns16550.c
> @@ -31,38 +31,6 @@
> #include <asm/fixmap.h>
> #endif
>
> -/*
> - * Configure serial port with a string:
> - * <baud>[/<base_baud>][,DPS[,<io-base>[,<irq>[,<port-bdf>[,<bridge-bdf>]]]]].
> - * The tail of the string can be omitted if platform defaults are sufficient.
> - * If the baud rate is pre-configured, perhaps by a bootloader, then 'auto'
> - * can be specified in place of a numeric baud rate. Polled mode is specified
> - * by requesting irq 0.
> - */
> -static char __initdata opt_com1[128] = "";
> -static char __initdata opt_com2[128] = "";
> -string_param("com1", opt_com1);
> -string_param("com2", opt_com2);
> -
> -enum serial_param_type {
> - baud,
> - clock_hz,
> - data_bits,
> - io_base,
> - irq,
> - parity,
> - reg_shift,
> - reg_width,
> - stop_bits,
> -#ifdef CONFIG_HAS_PCI
> - bridge_bdf,
> - device,
> - port_bdf,
> -#endif
> - /* List all parameters before this line. */
> - num_serial_params
> -};
> -
> static struct ns16550 {
> int baud, clock_hz, data_bits, parity, stop_bits, fifo_size, irq;
> u64 io_base; /* I/O port or memory-mapped I/O address. */
> @@ -98,32 +66,6 @@ static struct ns16550 {
> #endif
> } ns16550_com[2] = { { 0 } };
>
> -struct serial_param_var {
> - char name[12];
> - enum serial_param_type type;
> -};
> -
> -/*
> - * Enum struct keeping a table of all accepted parameter names for parsing
> - * com_console_options for serial port com1 and com2.
> - */
> -static const struct serial_param_var __initconst sp_vars[] = {
> - {"baud", baud},
> - {"clock-hz", clock_hz},
> - {"data-bits", data_bits},
> - {"io-base", io_base},
> - {"irq", irq},
> - {"parity", parity},
> - {"reg-shift", reg_shift},
> - {"reg-width", reg_width},
> - {"stop-bits", stop_bits},
> -#ifdef CONFIG_HAS_PCI
> - {"bridge", bridge_bdf},
> - {"dev", device},
> - {"port", port_bdf},
> -#endif
> -};
> -
> #ifdef CONFIG_HAS_PCI
> struct ns16550_config {
> u16 vendor_id;
> @@ -674,6 +616,19 @@ static struct uart_driver __read_mostly
> #endif
> };
>
> +static void ns16550_init_common(struct ns16550 *uart)
> +{
> + uart->clock_hz = UART_CLOCK_HZ;
> +
> + /* Default is no transmit FIFO. */
> + uart->fifo_size = 1;
> +
> + /* Default lsr_mask = UART_LSR_THRE */
> + uart->lsr_mask = UART_LSR_THRE;
> +}
> +
> +#ifdef CONFIG_X86
> +
> static int __init parse_parity_char(int c)
> {
> switch ( c )
> @@ -1217,6 +1172,64 @@ pci_uart_config(struct ns16550 *uart, bo
> #endif /* CONFIG_HAS_PCI */
>
> /*
> + * Configure serial port with a string:
> + * <baud>[/<base_baud>][,DPS[,<io-base>[,<irq>[,<port-bdf>[,<bridge-bdf>]]]]].
> + * The tail of the string can be omitted if platform defaults are sufficient.
> + * If the baud rate is pre-configured, perhaps by a bootloader, then 'auto'
> + * can be specified in place of a numeric baud rate. Polled mode is specified
> + * by requesting irq 0.
> + */
> +static char __initdata opt_com1[128] = "";
> +static char __initdata opt_com2[128] = "";
> +string_param("com1", opt_com1);
> +string_param("com2", opt_com2);
> +
> +enum serial_param_type {
> + baud,
> + clock_hz,
> + data_bits,
> + io_base,
> + irq,
> + parity,
> + reg_shift,
> + reg_width,
> + stop_bits,
> +#ifdef CONFIG_HAS_PCI
> + bridge_bdf,
> + device,
> + port_bdf,
> +#endif
> + /* List all parameters before this line. */
> + num_serial_params
> +};
> +
> +struct serial_param_var {
> + char name[12];
> + enum serial_param_type type;
> +};
> +
> +/*
> + * Enum struct keeping a table of all accepted parameter names for parsing
> + * com_console_options for serial port com1 and com2.
> + */
> +static const struct serial_param_var __initconst sp_vars[] = {
> + {"baud", baud},
> + {"clock-hz", clock_hz},
> + {"data-bits", data_bits},
> + {"io-base", io_base},
> + {"irq", irq},
> + {"parity", parity},
> + {"reg-shift", reg_shift},
> + {"reg-width", reg_width},
> + {"stop-bits", stop_bits},
> +#ifdef CONFIG_HAS_PCI
> + {"bridge", bridge_bdf},
> + {"dev", device},
> + {"port", port_bdf},
> +#endif
> +};
> +
> +/*
> * Used to parse name value pairs and return which value it is along with
> * pointer for the extracted value.
> */
> @@ -1504,17 +1517,6 @@ static void __init ns16550_parse_port_co
> serial_register_uart(uart - ns16550_com, &ns16550_driver, uart);
> }
>
> -static void ns16550_init_common(struct ns16550 *uart)
> -{
> - uart->clock_hz = UART_CLOCK_HZ;
> -
> - /* Default is no transmit FIFO. */
> - uart->fifo_size = 1;
> -
> - /* Default lsr_mask = UART_LSR_THRE */
> - uart->lsr_mask = UART_LSR_THRE;
> -}
> -
> void __init ns16550_init(int index, struct ns16550_defaults *defaults)
> {
> struct ns16550 *uart;
> @@ -1541,6 +1543,8 @@ void __init ns16550_init(int index, stru
> ns16550_parse_port_config(uart, (index == 0) ? opt_com1 : opt_com2);
> }
>
> +#endif /* CONFIG_X86 */
> +
> #ifdef CONFIG_HAS_DEVICE_TREE
> static int __init ns16550_uart_dt_init(struct dt_device_node *dev,
> const void *data)
>
Hello Jan,
> On 24 Nov 2020, at 12:11 am, Stefano Stabellini <sstabellini@kernel.org> wrote:
>
> On Mon, 23 Nov 2020, Jan Beulich wrote:
>> Pure code motion (plus the addition of "#ifdef CONFIG_X86); no
>> functional change intended.
>>
>> Reported-by: Julien Grall <julien@xen.org>
>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>
> Great cleanup
>
> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Reviewed-by: Rahul Singh <rahul.singh@arm.com>
Regards,
Rahul
>
>
>> ---
>> v2: Re-base over new earlier patch.
>>
>> --- a/docs/misc/xen-command-line.pandoc
>> +++ b/docs/misc/xen-command-line.pandoc
>> @@ -318,8 +318,8 @@ Interrupts. Specifying zero disables CM
>> Flag to indicate whether to probe for a CMOS Real Time Clock irrespective of
>> ACPI indicating none to be there.
>>
>> -### com1
>> -### com2
>> +### com1 (x86)
>> +### com2 (x86)
>>> `= <baud>[/<base-baud>][,[DPS][,[<io-base>|pci|amt][,[<irq>|msi][,[<port-bdf>][,[<bridge-bdf>]]]]]]`
>>
>> Both option `com1` and `com2` follow the same format.
>> --- a/xen/drivers/char/ns16550.c
>> +++ b/xen/drivers/char/ns16550.c
>> @@ -31,38 +31,6 @@
>> #include <asm/fixmap.h>
>> #endif
>>
>> -/*
>> - * Configure serial port with a string:
>> - * <baud>[/<base_baud>][,DPS[,<io-base>[,<irq>[,<port-bdf>[,<bridge-bdf>]]]]].
>> - * The tail of the string can be omitted if platform defaults are sufficient.
>> - * If the baud rate is pre-configured, perhaps by a bootloader, then 'auto'
>> - * can be specified in place of a numeric baud rate. Polled mode is specified
>> - * by requesting irq 0.
>> - */
>> -static char __initdata opt_com1[128] = "";
>> -static char __initdata opt_com2[128] = "";
>> -string_param("com1", opt_com1);
>> -string_param("com2", opt_com2);
>> -
>> -enum serial_param_type {
>> - baud,
>> - clock_hz,
>> - data_bits,
>> - io_base,
>> - irq,
>> - parity,
>> - reg_shift,
>> - reg_width,
>> - stop_bits,
>> -#ifdef CONFIG_HAS_PCI
>> - bridge_bdf,
>> - device,
>> - port_bdf,
>> -#endif
>> - /* List all parameters before this line. */
>> - num_serial_params
>> -};
>> -
>> static struct ns16550 {
>> int baud, clock_hz, data_bits, parity, stop_bits, fifo_size, irq;
>> u64 io_base; /* I/O port or memory-mapped I/O address. */
>> @@ -98,32 +66,6 @@ static struct ns16550 {
>> #endif
>> } ns16550_com[2] = { { 0 } };
>>
>> -struct serial_param_var {
>> - char name[12];
>> - enum serial_param_type type;
>> -};
>> -
>> -/*
>> - * Enum struct keeping a table of all accepted parameter names for parsing
>> - * com_console_options for serial port com1 and com2.
>> - */
>> -static const struct serial_param_var __initconst sp_vars[] = {
>> - {"baud", baud},
>> - {"clock-hz", clock_hz},
>> - {"data-bits", data_bits},
>> - {"io-base", io_base},
>> - {"irq", irq},
>> - {"parity", parity},
>> - {"reg-shift", reg_shift},
>> - {"reg-width", reg_width},
>> - {"stop-bits", stop_bits},
>> -#ifdef CONFIG_HAS_PCI
>> - {"bridge", bridge_bdf},
>> - {"dev", device},
>> - {"port", port_bdf},
>> -#endif
>> -};
>> -
>> #ifdef CONFIG_HAS_PCI
>> struct ns16550_config {
>> u16 vendor_id;
>> @@ -674,6 +616,19 @@ static struct uart_driver __read_mostly
>> #endif
>> };
>>
>> +static void ns16550_init_common(struct ns16550 *uart)
>> +{
>> + uart->clock_hz = UART_CLOCK_HZ;
>> +
>> + /* Default is no transmit FIFO. */
>> + uart->fifo_size = 1;
>> +
>> + /* Default lsr_mask = UART_LSR_THRE */
>> + uart->lsr_mask = UART_LSR_THRE;
>> +}
>> +
>> +#ifdef CONFIG_X86
>> +
>> static int __init parse_parity_char(int c)
>> {
>> switch ( c )
>> @@ -1217,6 +1172,64 @@ pci_uart_config(struct ns16550 *uart, bo
>> #endif /* CONFIG_HAS_PCI */
>>
>> /*
>> + * Configure serial port with a string:
>> + * <baud>[/<base_baud>][,DPS[,<io-base>[,<irq>[,<port-bdf>[,<bridge-bdf>]]]]].
>> + * The tail of the string can be omitted if platform defaults are sufficient.
>> + * If the baud rate is pre-configured, perhaps by a bootloader, then 'auto'
>> + * can be specified in place of a numeric baud rate. Polled mode is specified
>> + * by requesting irq 0.
>> + */
>> +static char __initdata opt_com1[128] = "";
>> +static char __initdata opt_com2[128] = "";
>> +string_param("com1", opt_com1);
>> +string_param("com2", opt_com2);
>> +
>> +enum serial_param_type {
>> + baud,
>> + clock_hz,
>> + data_bits,
>> + io_base,
>> + irq,
>> + parity,
>> + reg_shift,
>> + reg_width,
>> + stop_bits,
>> +#ifdef CONFIG_HAS_PCI
>> + bridge_bdf,
>> + device,
>> + port_bdf,
>> +#endif
>> + /* List all parameters before this line. */
>> + num_serial_params
>> +};
>> +
>> +struct serial_param_var {
>> + char name[12];
>> + enum serial_param_type type;
>> +};
>> +
>> +/*
>> + * Enum struct keeping a table of all accepted parameter names for parsing
>> + * com_console_options for serial port com1 and com2.
>> + */
>> +static const struct serial_param_var __initconst sp_vars[] = {
>> + {"baud", baud},
>> + {"clock-hz", clock_hz},
>> + {"data-bits", data_bits},
>> + {"io-base", io_base},
>> + {"irq", irq},
>> + {"parity", parity},
>> + {"reg-shift", reg_shift},
>> + {"reg-width", reg_width},
>> + {"stop-bits", stop_bits},
>> +#ifdef CONFIG_HAS_PCI
>> + {"bridge", bridge_bdf},
>> + {"dev", device},
>> + {"port", port_bdf},
>> +#endif
>> +};
>> +
>> +/*
>> * Used to parse name value pairs and return which value it is along with
>> * pointer for the extracted value.
>> */
>> @@ -1504,17 +1517,6 @@ static void __init ns16550_parse_port_co
>> serial_register_uart(uart - ns16550_com, &ns16550_driver, uart);
>> }
>>
>> -static void ns16550_init_common(struct ns16550 *uart)
>> -{
>> - uart->clock_hz = UART_CLOCK_HZ;
>> -
>> - /* Default is no transmit FIFO. */
>> - uart->fifo_size = 1;
>> -
>> - /* Default lsr_mask = UART_LSR_THRE */
>> - uart->lsr_mask = UART_LSR_THRE;
>> -}
>> -
>> void __init ns16550_init(int index, struct ns16550_defaults *defaults)
>> {
>> struct ns16550 *uart;
>> @@ -1541,6 +1543,8 @@ void __init ns16550_init(int index, stru
>> ns16550_parse_port_config(uart, (index == 0) ? opt_com1 : opt_com2);
>> }
>>
>> +#endif /* CONFIG_X86 */
>> +
>> #ifdef CONFIG_HAS_DEVICE_TREE
>> static int __init ns16550_uart_dt_init(struct dt_device_node *dev,
>> const void *data)
>>
>
There's no point wrapping the function invocation when
- the function body is already suitably wrapped,
- the function itself is unconditionally available.
Reported-by: Julien Grall <julien@xen.org>
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/drivers/char/ns16550.c
+++ b/xen/drivers/char/ns16550.c
@@ -662,9 +662,7 @@ static int __init check_existence(struct
return 1; /* Everything is MMIO */
#endif
-#ifdef CONFIG_HAS_PCI
pci_serial_early_init(uart);
-#endif
/*
* Do a simple existence test first; if we fail this,
On Mon, 23 Nov 2020, Jan Beulich wrote: > There's no point wrapping the function invocation when > - the function body is already suitably wrapped, > - the function itself is unconditionally available. > > Reported-by: Julien Grall <julien@xen.org> > Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> > --- a/xen/drivers/char/ns16550.c > +++ b/xen/drivers/char/ns16550.c > @@ -662,9 +662,7 @@ static int __init check_existence(struct > return 1; /* Everything is MMIO */ > #endif > > -#ifdef CONFIG_HAS_PCI > pci_serial_early_init(uart); > -#endif > > /* > * Do a simple existence test first; if we fail this, >
Hello , > On 24 Nov 2020, at 12:11 am, Stefano Stabellini <sstabellini@kernel.org> wrote: > > On Mon, 23 Nov 2020, Jan Beulich wrote: >> There's no point wrapping the function invocation when >> - the function body is already suitably wrapped, >> - the function itself is unconditionally available. >> >> Reported-by: Julien Grall <julien@xen.org> >> Signed-off-by: Jan Beulich <jbeulich@suse.com> > > Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> > Reviewed-by: Rahul Singh <rahul.singh@arm.com> > >> --- a/xen/drivers/char/ns16550.c >> +++ b/xen/drivers/char/ns16550.c >> @@ -662,9 +662,7 @@ static int __init check_existence(struct >> return 1; /* Everything is MMIO */ >> #endif >> >> -#ifdef CONFIG_HAS_PCI >> pci_serial_early_init(uart); >> -#endif >> >> /* >> * Do a simple existence test first; if we fail this, >> > Regards, Rahul
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