It's all the same for the 3 arch-es which have it, and RISC-V would
introduce a 4th instance. Put it in xen/smp.h instead, while still
permitting asm/smp.h to define a custom variant if need be.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/arch/arm/include/asm/smp.h
+++ b/xen/arch/arm/include/asm/smp.h
@@ -12,8 +12,6 @@ extern unsigned long smp_up_cpu;
DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_mask);
DECLARE_PER_CPU(cpumask_var_t, cpu_core_mask);
-#define cpu_is_offline(cpu) unlikely(!cpu_online(cpu))
-
/*
* Do we, for platform reasons, need to actually keep CPUs online when we
* would otherwise prefer them to be off?
--- a/xen/arch/ppc/include/asm/smp.h
+++ b/xen/arch/ppc/include/asm/smp.h
@@ -7,8 +7,6 @@
DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_mask);
DECLARE_PER_CPU(cpumask_var_t, cpu_core_mask);
-#define cpu_is_offline(cpu) unlikely(!cpu_online(cpu))
-
/*
* Do we, for platform reasons, need to actually keep CPUs online when we
* would otherwise prefer them to be off?
--- a/xen/arch/x86/include/asm/smp.h
+++ b/xen/arch/x86/include/asm/smp.h
@@ -43,7 +43,6 @@ extern u32 x86_cpu_to_apicid[];
#define cpu_physical_id(cpu) x86_cpu_to_apicid[cpu]
-#define cpu_is_offline(cpu) unlikely(!cpu_online(cpu))
extern void cpu_exit_clear(unsigned int cpu);
extern void cpu_uninit(unsigned int cpu);
int cpu_add(uint32_t apic_id, uint32_t acpi_id, uint32_t pxm);
--- a/xen/include/xen/smp.h
+++ b/xen/include/xen/smp.h
@@ -3,6 +3,10 @@
#include <asm/smp.h>
+#ifndef cpu_is_offline
+#define cpu_is_offline(cpu) unlikely(!cpu_online(cpu))
+#endif
+
/*
* stops all CPUs but the current one:
*/
Hi Jan, On 13/12/2023 11:26, Jan Beulich wrote: > It's all the same for the 3 arch-es which have it, and RISC-V would > introduce a 4th instance. Put it in xen/smp.h instead, while still > permitting asm/smp.h to define a custom variant if need be. > > Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Julien Grall <jgrall@amazon.com> Cheers, -- Julien Grall
Hi Jan, On 12/13/23 5:26 AM, Jan Beulich wrote: > It's all the same for the 3 arch-es which have it, and RISC-V would > introduce a 4th instance. Put it in xen/smp.h instead, while still > permitting asm/smp.h to define a custom variant if need be. > > Signed-off-by: Jan Beulich <jbeulich@suse.com> > Acked-by: Shawn Anastasio <sanastasio@raptorengineering.com> Thanks, Shawn
On Wed, 2023-12-13 at 12:26 +0100, Jan Beulich wrote: > It's all the same for the 3 arch-es which have it, and RISC-V would > introduce a 4th instance. Put it in xen/smp.h instead, while still > permitting asm/smp.h to define a custom variant if need be. > > Signed-off-by: Jan Beulich <jbeulich@suse.com> > > --- a/xen/arch/arm/include/asm/smp.h > +++ b/xen/arch/arm/include/asm/smp.h > @@ -12,8 +12,6 @@ extern unsigned long smp_up_cpu; > DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_mask); > DECLARE_PER_CPU(cpumask_var_t, cpu_core_mask); > > -#define cpu_is_offline(cpu) unlikely(!cpu_online(cpu)) > - > /* > * Do we, for platform reasons, need to actually keep CPUs online > when we > * would otherwise prefer them to be off? > --- a/xen/arch/ppc/include/asm/smp.h > +++ b/xen/arch/ppc/include/asm/smp.h > @@ -7,8 +7,6 @@ > DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_mask); > DECLARE_PER_CPU(cpumask_var_t, cpu_core_mask); > > -#define cpu_is_offline(cpu) unlikely(!cpu_online(cpu)) > - > /* > * Do we, for platform reasons, need to actually keep CPUs online > when we > * would otherwise prefer them to be off? > --- a/xen/arch/x86/include/asm/smp.h > +++ b/xen/arch/x86/include/asm/smp.h > @@ -43,7 +43,6 @@ extern u32 x86_cpu_to_apicid[]; > > #define cpu_physical_id(cpu) x86_cpu_to_apicid[cpu] > > -#define cpu_is_offline(cpu) unlikely(!cpu_online(cpu)) > extern void cpu_exit_clear(unsigned int cpu); > extern void cpu_uninit(unsigned int cpu); > int cpu_add(uint32_t apic_id, uint32_t acpi_id, uint32_t pxm); > --- a/xen/include/xen/smp.h > +++ b/xen/include/xen/smp.h > @@ -3,6 +3,10 @@ > > #include <asm/smp.h> > > +#ifndef cpu_is_offline > +#define cpu_is_offline(cpu) unlikely(!cpu_online(cpu)) > +#endif > + > /* > * stops all CPUs but the current one: > */ Reviewed-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
On Wed, Dec 13, 2023 at 11:26 AM Jan Beulich <jbeulich@suse.com> wrote: > > It's all the same for the 3 arch-es which have it, and RISC-V would > introduce a 4th instance. Put it in xen/smp.h instead, while still > permitting asm/smp.h to define a custom variant if need be. > > Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: George Dunlap <george.dunlap@cloud.com>
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