With there now being a CPUID field for this, let's try to avoid further
growing the set of family-specific "magic" numbers. Sadly on the boot
CPU it's too early to use the host policy, so an actual CPUID insn needs
to be issued. Let's take the opportunity though and make the extended
CPUID level available early.

Signed-off-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -352,7 +352,9 @@ void __init early_cpu_init(void)
 			    &c->x86_capability[FEATURESET_7d0]);
 
 	eax = cpuid_eax(0x80000000);
-	if ((eax >> 16) == 0x8000 && eax >= 0x80000008) {
+	if ((eax >> 16) == 0x8000)
+		c->extended_cpuid_level = eax;
+	if (c->extended_cpuid_level >= 0x80000008) {
 		ebx = eax >= 0x8000001f ? cpuid_ebx(0x8000001f) : 0;
 		eax = cpuid_eax(0x80000008);
 
--- a/xen/arch/x86/cpu/microcode/amd.c
+++ b/xen/arch/x86/cpu/microcode/amd.c
@@ -108,6 +108,13 @@ static bool verify_patch_size(uint32_t p
 {
     uint32_t max_size;
 
+    if ( boot_cpu_data.extended_cpuid_level >= 0x80000021 )
+    {
+        max_size = cpuid_ebx(0x80000021) & 0xfff;
+        if ( max_size )
+            return patch_size <= (max_size << 4);
+    }
+
 #define F1XH_MPB_MAX_SIZE 2048
 #define F14H_MPB_MAX_SIZE 1824
 #define F15H_MPB_MAX_SIZE 4096