This series adds two pieces of Functional Safety documentation under
docs/fusa/.

Patch 1 introduces docs/fusa/coverage_gap.rst, a table that records the
code regions excluded from the coverage report because they are
unreachable by design. Code that no test can reach (for example a
defensive default arm of a switch that no caller can reach) would
otherwise show up as a permanent coverage gap even though it is correct.
Each exclusion is given a stable id, the excluded source location, and a
justification stating why the code is unreachable and what would make it
reachable again, so that a genuine gap is never hidden behind an LCOV
marker. The two vGICv3 default arms are documented as the first entries.

Patch 2 adds the arm64 generic timer architecture specification under
docs/fusa/architecture_specs/. An architecture spec is a prose document
that explains how Xen uses a piece of hardware -- what the hardware
does, which parts Xen drives directly, which parts it emulates for a
guest, and how they interact over the lifetime of a VM. This one covers
the Arm Generic Timer and traces to the existing
XenSwdgn~arm64_generic_timer_* design requirements.

Both documents are wired into the docs/fusa Sphinx toctree.

Ayan Kumar Halder (2):
  docs/fusa: add coverage_gap.rst tabulating vGICv3 LCOV exclusions
  docs/fusa: add generic timer arch spec with ASCII diagrams

 .../fusa/architecture_specs/generic_timer.rst | 215 ++++++++++++++++++
 docs/fusa/architecture_specs/index.rst        |   9 +
 docs/fusa/coverage_gap.rst                    |  41 ++++
 docs/fusa/index.rst                           |   2 +
 4 files changed, 267 insertions(+)
 create mode 100644 docs/fusa/architecture_specs/generic_timer.rst
 create mode 100644 docs/fusa/architecture_specs/index.rst
 create mode 100644 docs/fusa/coverage_gap.rst

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2.25.1