struct cpuinfo_x86
.x86 => .family
.x86_vendor => .vendor
.x86_model => .model
.x86_mask => .stepping
No functional change.
This work is part of making Xen safe for Intel family 18/19.
Signed-off-by: Kevin Lampis <kevin.lampis@citrix.com>
---
I couldn't find any information about these Intel family 6 processors:
model 0x5d: /* SoFIA 3G Granite/ES2.1 */
model 0x65: /* SoFIA LTE AOSP */
model 0x6e: /* Cougar Mountain */
Should I add them to intel-family.h?
---
xen/arch/x86/hvm/hvm.c | 2 +-
xen/arch/x86/hvm/svm/svm.c | 6 +-
xen/arch/x86/hvm/vmx/vmcs.c | 4 +-
xen/arch/x86/hvm/vmx/vmx.c | 278 ++++++++++++++++++------------------
4 files changed, 144 insertions(+), 146 deletions(-)
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 4d37a93c57..6ad52e1197 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -3850,7 +3850,7 @@ void hvm_ud_intercept(struct cpu_user_regs *regs)
{
struct vcpu *cur = current;
bool should_emulate =
- cur->domain->arch.cpuid->x86_vendor != boot_cpu_data.x86_vendor;
+ cur->domain->arch.cpuid->x86_vendor != boot_cpu_data.vendor;
struct hvm_emulate_ctxt ctxt;
hvm_emulate_init_once(&ctxt, opt_hvm_fep ? NULL : is_cross_vendor, regs);
diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index 18ba837738..1320abe392 100644
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -590,7 +590,7 @@ static void cf_check svm_cpuid_policy_changed(struct vcpu *v)
u32 bitmap = vmcb_get_exception_intercepts(vmcb);
if ( opt_hvm_fep ||
- (v->domain->arch.cpuid->x86_vendor != boot_cpu_data.x86_vendor) )
+ (v->domain->arch.cpuid->x86_vendor != boot_cpu_data.vendor) )
bitmap |= (1U << X86_EXC_UD);
else
bitmap &= ~(1U << X86_EXC_UD);
@@ -1057,7 +1057,7 @@ static void svm_guest_osvw_init(struct domain *d)
* be conservative here and therefore we tell the guest that erratum 298
* is present (because we really don't know).
*/
- if ( osvw_length == 0 && boot_cpu_data.x86 == 0x10 )
+ if ( osvw_length == 0 && boot_cpu_data.family == 0x10 )
svm->osvw.status |= 1;
spin_unlock(&osvw_lock);
@@ -1791,7 +1791,7 @@ static int cf_check svm_msr_read_intercept(
if ( !rdmsr_safe(msr, msr_content) )
break;
- if ( boot_cpu_data.x86 == 0xf )
+ if ( boot_cpu_data.family == 0xf )
{
/*
* Win2k8 x64 reads this MSR on revF chips, where it wasn't
diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
index c2e7f9aed3..d3b1730f1d 100644
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -26,6 +26,7 @@
#include <asm/hvm/vmx/vmx.h>
#include <asm/hvm/vmx/vvmx.h>
#include <asm/idt.h>
+#include <asm/intel-family.h>
#include <asm/monitor.h>
#include <asm/msr.h>
#include <asm/processor.h>
@@ -2163,8 +2164,7 @@ int __init vmx_vmcs_init(void)
if ( opt_ept_ad < 0 )
/* Work around Erratum AVR41 on Avoton processors. */
- opt_ept_ad = !(boot_cpu_data.x86 == 6 &&
- boot_cpu_data.x86_model == 0x4d);
+ opt_ept_ad = !(boot_cpu_data.vfm == INTEL_ATOM_SILVERMONT_D);
ret = _vmx_cpu_up(true);
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 82c55f49ae..c332d5078d 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -34,6 +34,7 @@
#include <asm/hvm/vmx/vmcs.h>
#include <asm/hvm/vmx/vmx.h>
#include <asm/hvm/vpt.h>
+#include <asm/intel-family.h>
#include <asm/io.h>
#include <asm/iocap.h>
#include <asm/mce.h>
@@ -502,72 +503,75 @@ static const struct lbr_info *__ro_after_init model_specific_lbr;
static const struct lbr_info *__init get_model_specific_lbr(void)
{
- switch ( boot_cpu_data.x86 )
+ switch ( boot_cpu_data.vfm )
{
- case 6:
- switch ( boot_cpu_data.x86_model )
- {
- /* Core2 Duo */
- case 0x0f:
- /* Enhanced Core */
- case 0x17:
- /* Xeon 7400 */
- case 0x1d:
- return c2_lbr;
- /* Nehalem */
- case 0x1a: case 0x1e: case 0x1f: case 0x2e:
- /* Westmere */
- case 0x25: case 0x2c: case 0x2f:
- /* Sandy Bridge */
- case 0x2a: case 0x2d:
- /* Ivy Bridge */
- case 0x3a: case 0x3e:
- /* Haswell */
- case 0x3c: case 0x3f: case 0x45: case 0x46:
- /* Broadwell */
- case 0x3d: case 0x47: case 0x4f: case 0x56:
- return nh_lbr;
- /* Skylake */
- case 0x4e: case 0x5e:
- /* Xeon Scalable */
- case 0x55:
- /* Cannon Lake */
- case 0x66:
- /* Goldmont Plus */
- case 0x7a:
- /* Ice Lake */
- case 0x6a: case 0x6c: case 0x7d: case 0x7e:
- /* Tiger Lake */
- case 0x8c: case 0x8d:
- /* Tremont */
- case 0x86:
- /* Kaby Lake */
- case 0x8e: case 0x9e:
- /* Comet Lake */
- case 0xa5: case 0xa6:
- return sk_lbr;
- /* Atom */
- case 0x1c: case 0x26: case 0x27: case 0x35: case 0x36:
- return at_lbr;
- /* Silvermont */
- case 0x37: case 0x4a: case 0x4d: case 0x5a: case 0x5d:
- /* Airmont */
- case 0x4c:
- return sm_lbr;
- /* Goldmont */
- case 0x5c: case 0x5f:
- return gm_lbr;
- }
- break;
-
- case 15:
- switch ( boot_cpu_data.x86_model )
- {
- /* Pentium4/Xeon with em64t */
- case 3: case 4: case 6:
- return p4_lbr;
- }
- break;
+ case INTEL_CORE2_DUNNINGTON:
+ case INTEL_CORE2_MEROM:
+ case INTEL_CORE2_PENRYN:
+ return c2_lbr;
+
+ case INTEL_NEHALEM:
+ case INTEL_NEHALEM_EP:
+ case INTEL_NEHALEM_EX:
+ case INTEL_NEHALEM_G:
+ case INTEL_WESTMERE:
+ case INTEL_WESTMERE_EP:
+ case INTEL_WESTMERE_EX:
+ case INTEL_SANDYBRIDGE:
+ case INTEL_SANDYBRIDGE_X:
+ case INTEL_IVYBRIDGE:
+ case INTEL_IVYBRIDGE_X:
+ case INTEL_HASWELL:
+ case INTEL_HASWELL_G:
+ case INTEL_HASWELL_L:
+ case INTEL_HASWELL_X:
+ case INTEL_BROADWELL:
+ case INTEL_BROADWELL_D:
+ case INTEL_BROADWELL_G:
+ case INTEL_BROADWELL_X:
+ return nh_lbr;
+
+ case INTEL_SKYLAKE:
+ case INTEL_SKYLAKE_L:
+ case INTEL_SKYLAKE_X:
+ case INTEL_CANNONLAKE_L:
+ case INTEL_ATOM_GOLDMONT_PLUS:
+ case INTEL_ICELAKE:
+ case INTEL_ICELAKE_D:
+ case INTEL_ICELAKE_L:
+ case INTEL_ICELAKE_X:
+ case INTEL_TIGERLAKE:
+ case INTEL_TIGERLAKE_L:
+ case INTEL_ATOM_TREMONT_D:
+ case INTEL_KABYLAKE:
+ case INTEL_KABYLAKE_L:
+ case INTEL_COMETLAKE:
+ case INTEL_COMETLAKE_L:
+ return sk_lbr;
+
+ case INTEL_ATOM_BONNELL:
+ case INTEL_ATOM_BONNELL_MID:
+ case INTEL_ATOM_SALTWELL:
+ case INTEL_ATOM_SALTWELL_MID:
+ case INTEL_ATOM_SALTWELL_TABLET:
+ return at_lbr;
+
+ case INTEL_ATOM_SILVERMONT:
+ case INTEL_ATOM_SILVERMONT_MID:
+ case INTEL_ATOM_SILVERMONT_D:
+ case INTEL_ATOM_SILVERMONT_MID2:
+ //case 0x5d: // XXX
+ case INTEL_ATOM_AIRMONT:
+ return sm_lbr;
+
+ case INTEL_ATOM_GOLDMONT:
+ case INTEL_ATOM_GOLDMONT_D:
+ return gm_lbr;
+
+ case INTEL_P4_PRESCOTT:
+ case INTEL_P4_PRESCOTT_2M:
+ case INTEL_P4_CEDARMILL:
+ return p4_lbr;
}
return NULL;
@@ -804,7 +808,7 @@ static void cf_check vmx_cpuid_policy_changed(struct vcpu *v)
int rc = 0;
if ( opt_hvm_fep ||
- (v->domain->arch.cpuid->x86_vendor != boot_cpu_data.x86_vendor) )
+ (v->domain->arch.cpuid->x86_vendor != boot_cpu_data.vendor) )
v->arch.hvm.vmx.exception_bitmap |= (1U << X86_EXC_UD);
else
v->arch.hvm.vmx.exception_bitmap &= ~(1U << X86_EXC_UD);
@@ -3073,71 +3077,71 @@ static bool __init has_if_pschange_mc(void)
* IF_PSCHANGE_MC is only known to affect Intel Family 6 processors at
* this time.
*/
- if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
- boot_cpu_data.x86 != 6 )
+ if ( boot_cpu_data.vendor != X86_VENDOR_INTEL ||
+ boot_cpu_data.family != 6 )
return false;
- switch ( boot_cpu_data.x86_model )
+ switch ( boot_cpu_data.vfm )
{
/*
* Core processors since at least Nehalem are vulnerable.
*/
- case 0x1f: /* Auburndale / Havendale */
- case 0x1e: /* Nehalem */
- case 0x1a: /* Nehalem EP */
- case 0x2e: /* Nehalem EX */
- case 0x25: /* Westmere */
- case 0x2c: /* Westmere EP */
- case 0x2f: /* Westmere EX */
- case 0x2a: /* SandyBridge */
- case 0x2d: /* SandyBridge EP/EX */
- case 0x3a: /* IvyBridge */
- case 0x3e: /* IvyBridge EP/EX */
- case 0x3c: /* Haswell */
- case 0x3f: /* Haswell EX/EP */
- case 0x45: /* Haswell D */
- case 0x46: /* Haswell H */
- case 0x3d: /* Broadwell */
- case 0x47: /* Broadwell H */
- case 0x4f: /* Broadwell EP/EX */
- case 0x56: /* Broadwell D */
- case 0x4e: /* Skylake M */
- case 0x5e: /* Skylake D */
- case 0x55: /* Skylake-X / Cascade Lake */
- case 0x7d: /* Ice Lake */
- case 0x7e: /* Ice Lake */
- case 0x8e: /* Kaby / Coffee / Whiskey Lake M */
- case 0x9e: /* Kaby / Coffee / Whiskey Lake D */
- case 0xa5: /* Comet Lake H/S */
- case 0xa6: /* Comet Lake U */
+ case INTEL_NEHALEM_G:
+ case INTEL_NEHALEM:
+ case INTEL_NEHALEM_EP:
+ case INTEL_NEHALEM_EX:
+ case INTEL_WESTMERE:
+ case INTEL_WESTMERE_EP:
+ case INTEL_WESTMERE_EX:
+ case INTEL_SANDYBRIDGE:
+ case INTEL_SANDYBRIDGE_X:
+ case INTEL_IVYBRIDGE:
+ case INTEL_IVYBRIDGE_X:
+ case INTEL_HASWELL:
+ case INTEL_HASWELL_X:
+ case INTEL_HASWELL_L:
+ case INTEL_HASWELL_G:
+ case INTEL_BROADWELL:
+ case INTEL_BROADWELL_G:
+ case INTEL_BROADWELL_X:
+ case INTEL_BROADWELL_D:
+ case INTEL_SKYLAKE_L:
+ case INTEL_SKYLAKE:
+ case INTEL_SKYLAKE_X:
+ case INTEL_ICELAKE:
+ case INTEL_ICELAKE_L:
+ case INTEL_KABYLAKE_L:
+ case INTEL_KABYLAKE:
+ case INTEL_COMETLAKE:
+ case INTEL_COMETLAKE_L:
return true;
/*
* Atom processors are not vulnerable.
*/
- case 0x1c: /* Pineview */
- case 0x26: /* Lincroft */
- case 0x27: /* Penwell */
- case 0x35: /* Cloverview */
- case 0x36: /* Cedarview */
- case 0x37: /* Baytrail / Valleyview (Silvermont) */
- case 0x4d: /* Avaton / Rangely (Silvermont) */
- case 0x4c: /* Cherrytrail / Brasswell */
- case 0x4a: /* Merrifield */
- case 0x5a: /* Moorefield */
- case 0x5c: /* Goldmont */
- case 0x5d: /* SoFIA 3G Granite/ES2.1 */
- case 0x65: /* SoFIA LTE AOSP */
- case 0x5f: /* Denverton */
- case 0x6e: /* Cougar Mountain */
- case 0x75: /* Lightning Mountain */
- case 0x7a: /* Gemini Lake */
- case 0x86: /* Jacobsville */
+ case INTEL_ATOM_BONNELL:
+ case INTEL_ATOM_BONNELL_MID:
+ case INTEL_ATOM_SALTWELL_MID:
+ case INTEL_ATOM_SALTWELL_TABLET:
+ case INTEL_ATOM_SALTWELL:
+ case INTEL_ATOM_SILVERMONT:
+ case INTEL_ATOM_SILVERMONT_D:
+ case INTEL_ATOM_AIRMONT:
+ case INTEL_ATOM_SILVERMONT_MID:
+ case INTEL_ATOM_SILVERMONT_MID2:
+ case INTEL_ATOM_GOLDMONT:
+ //case 0x5d: /* SoFIA 3G Granite/ES2.1 */ // XXX ???
+ //case 0x65: /* SoFIA LTE AOSP */ // XXX ???
+ case INTEL_ATOM_GOLDMONT_D:
+ //case 0x6e: /* Cougar Mountain */ // XXX ???
+ case INTEL_ATOM_AIRMONT_NP:
+ case INTEL_ATOM_GOLDMONT_PLUS:
+ case INTEL_ATOM_TREMONT_D:
return false;
default:
printk("Unrecognised CPU model %#x - assuming vulnerable to IF_PSCHANGE_MC\n",
- boot_cpu_data.x86_model);
+ boot_cpu_data.model);
return true;
}
}
@@ -3431,23 +3435,20 @@ static void __init lbr_tsx_fixup_check(void)
* fixed up as well.
*/
if ( cpu_has_hle || cpu_has_rtm ||
- boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
- boot_cpu_data.x86 != 6 )
+ boot_cpu_data.vendor != X86_VENDOR_INTEL ||
+ boot_cpu_data.family != 6 )
return;
- switch ( boot_cpu_data.x86_model )
+ switch ( boot_cpu_data.vfm )
{
- case 0x3c: /* HSM182, HSD172 - 4th gen Core */
- case 0x3f: /* HSE117 - Xeon E5 v3 */
- case 0x45: /* HSM182 - 4th gen Core */
- case 0x46: /* HSM182, HSD172 - 4th gen Core (GT3) */
- case 0x3d: /* BDM127 - 5th gen Core */
- case 0x47: /* BDD117 - 5th gen Core (GT3)
- BDW117 - Xeon E3-1200 v4 */
- case 0x4f: /* BDF85 - Xeon E5-2600 v4
- BDH75 - Core-i7 for LGA2011-v3 Socket
- BDX88 - Xeon E7-x800 v4 */
- case 0x56: /* BDE105 - Xeon D-1500 */
+ case INTEL_HASWELL:
+ case INTEL_HASWELL_X:
+ case INTEL_HASWELL_L:
+ case INTEL_HASWELL_G:
+ case INTEL_BROADWELL:
+ case INTEL_BROADWELL_G:
+ case INTEL_BROADWELL_X:
+ case INTEL_BROADWELL_D:
break;
default:
return;
@@ -3476,19 +3477,16 @@ static void __init ler_to_fixup_check(void)
* that are not equal to bit[47]. Attempting to context switch this value
* may cause a #GP. Software should sign extend the MSR.
*/
- if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
- boot_cpu_data.x86 != 6 )
+ if ( boot_cpu_data.vendor != X86_VENDOR_INTEL ||
+ boot_cpu_data.family != 6 )
return;
- switch ( boot_cpu_data.x86_model )
+ switch ( boot_cpu_data.vfm )
{
- case 0x3d: /* BDM131 - 5th gen Core */
- case 0x47: /* BDD??? - 5th gen Core (H-Processor line)
- BDW120 - Xeon E3-1200 v4 */
- case 0x4f: /* BDF93 - Xeon E5-2600 v4
- BDH80 - Core-i7 for LGA2011-v3 Socket
- BDX93 - Xeon E7-x800 v4 */
- case 0x56: /* BDE??? - Xeon D-1500 */
+ case INTEL_BROADWELL:
+ case INTEL_BROADWELL_G:
+ case INTEL_BROADWELL_X:
+ case INTEL_BROADWELL_D:
ler_to_fixup_needed = true;
break;
}
--
2.51.1On 04.03.2026 20:53, Kevin Lampis wrote:
> struct cpuinfo_x86
> .x86 => .family
> .x86_vendor => .vendor
> .x86_model => .model
> .x86_mask => .stepping
>
> No functional change.
>
> This work is part of making Xen safe for Intel family 18/19.
>
> Signed-off-by: Kevin Lampis <kevin.lampis@citrix.com>
> ---
> I couldn't find any information about these Intel family 6 processors:
> model 0x5d: /* SoFIA 3G Granite/ES2.1 */
> model 0x65: /* SoFIA LTE AOSP */
> model 0x6e: /* Cougar Mountain */
> Should I add them to intel-family.h?
We should keep that in sync with Linux, I think, so "no" unless you mean to
first have respective entries added there.
0x5d is listed in the SDM, so I'd recommend keeping the entries (using IFM()
directly for the time being).
0x65 and 0x6e aren't listed in the SDM, so may never really have hit the
public. Respective cases can perhaps be dropped, but such dropping would
again likely better be done in a separate change.
> @@ -3073,71 +3077,71 @@ static bool __init has_if_pschange_mc(void)
> * IF_PSCHANGE_MC is only known to affect Intel Family 6 processors at
> * this time.
> */
> - if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
> - boot_cpu_data.x86 != 6 )
> + if ( boot_cpu_data.vendor != X86_VENDOR_INTEL ||
> + boot_cpu_data.family != 6 )
> return false;
>
> - switch ( boot_cpu_data.x86_model )
> + switch ( boot_cpu_data.vfm )
> {
> /*
> * Core processors since at least Nehalem are vulnerable.
> */
> - case 0x1f: /* Auburndale / Havendale */
> - case 0x1e: /* Nehalem */
> - case 0x1a: /* Nehalem EP */
> - case 0x2e: /* Nehalem EX */
> - case 0x25: /* Westmere */
> - case 0x2c: /* Westmere EP */
> - case 0x2f: /* Westmere EX */
> - case 0x2a: /* SandyBridge */
> - case 0x2d: /* SandyBridge EP/EX */
> - case 0x3a: /* IvyBridge */
> - case 0x3e: /* IvyBridge EP/EX */
> - case 0x3c: /* Haswell */
> - case 0x3f: /* Haswell EX/EP */
> - case 0x45: /* Haswell D */
> - case 0x46: /* Haswell H */
> - case 0x3d: /* Broadwell */
> - case 0x47: /* Broadwell H */
> - case 0x4f: /* Broadwell EP/EX */
> - case 0x56: /* Broadwell D */
> - case 0x4e: /* Skylake M */
> - case 0x5e: /* Skylake D */
> - case 0x55: /* Skylake-X / Cascade Lake */
> - case 0x7d: /* Ice Lake */
> - case 0x7e: /* Ice Lake */
> - case 0x8e: /* Kaby / Coffee / Whiskey Lake M */
> - case 0x9e: /* Kaby / Coffee / Whiskey Lake D */
> - case 0xa5: /* Comet Lake H/S */
> - case 0xa6: /* Comet Lake U */
> + case INTEL_NEHALEM_G:
> + case INTEL_NEHALEM:
> + case INTEL_NEHALEM_EP:
> + case INTEL_NEHALEM_EX:
> + case INTEL_WESTMERE:
> + case INTEL_WESTMERE_EP:
> + case INTEL_WESTMERE_EX:
> + case INTEL_SANDYBRIDGE:
> + case INTEL_SANDYBRIDGE_X:
> + case INTEL_IVYBRIDGE:
> + case INTEL_IVYBRIDGE_X:
> + case INTEL_HASWELL:
> + case INTEL_HASWELL_X:
> + case INTEL_HASWELL_L:
> + case INTEL_HASWELL_G:
> + case INTEL_BROADWELL:
> + case INTEL_BROADWELL_G:
> + case INTEL_BROADWELL_X:
> + case INTEL_BROADWELL_D:
> + case INTEL_SKYLAKE_L:
> + case INTEL_SKYLAKE:
> + case INTEL_SKYLAKE_X:
> + case INTEL_ICELAKE:
> + case INTEL_ICELAKE_L:
> + case INTEL_KABYLAKE_L:
> + case INTEL_KABYLAKE:
> + case INTEL_COMETLAKE:
> + case INTEL_COMETLAKE_L:
> return true;
>
> /*
> * Atom processors are not vulnerable.
> */
> - case 0x1c: /* Pineview */
> - case 0x26: /* Lincroft */
> - case 0x27: /* Penwell */
> - case 0x35: /* Cloverview */
> - case 0x36: /* Cedarview */
> - case 0x37: /* Baytrail / Valleyview (Silvermont) */
> - case 0x4d: /* Avaton / Rangely (Silvermont) */
> - case 0x4c: /* Cherrytrail / Brasswell */
> - case 0x4a: /* Merrifield */
> - case 0x5a: /* Moorefield */
> - case 0x5c: /* Goldmont */
> - case 0x5d: /* SoFIA 3G Granite/ES2.1 */
> - case 0x65: /* SoFIA LTE AOSP */
> - case 0x5f: /* Denverton */
> - case 0x6e: /* Cougar Mountain */
> - case 0x75: /* Lightning Mountain */
> - case 0x7a: /* Gemini Lake */
> - case 0x86: /* Jacobsville */
> + case INTEL_ATOM_BONNELL:
> + case INTEL_ATOM_BONNELL_MID:
> + case INTEL_ATOM_SALTWELL_MID:
> + case INTEL_ATOM_SALTWELL_TABLET:
> + case INTEL_ATOM_SALTWELL:
> + case INTEL_ATOM_SILVERMONT:
> + case INTEL_ATOM_SILVERMONT_D:
> + case INTEL_ATOM_AIRMONT:
> + case INTEL_ATOM_SILVERMONT_MID:
> + case INTEL_ATOM_SILVERMONT_MID2:
Can the Silvermonts please be grouped together?
> + case INTEL_ATOM_GOLDMONT:
> + //case 0x5d: /* SoFIA 3G Granite/ES2.1 */ // XXX ???
> + //case 0x65: /* SoFIA LTE AOSP */ // XXX ???
> + case INTEL_ATOM_GOLDMONT_D:
> + //case 0x6e: /* Cougar Mountain */ // XXX ???
> + case INTEL_ATOM_AIRMONT_NP:
Same for the Airmonts and ...
> + case INTEL_ATOM_GOLDMONT_PLUS:
... the Goldmonts.
> @@ -3431,23 +3435,20 @@ static void __init lbr_tsx_fixup_check(void)
> * fixed up as well.
> */
> if ( cpu_has_hle || cpu_has_rtm ||
> - boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
> - boot_cpu_data.x86 != 6 )
> + boot_cpu_data.vendor != X86_VENDOR_INTEL ||
> + boot_cpu_data.family != 6 )
> return;
>
> - switch ( boot_cpu_data.x86_model )
> + switch ( boot_cpu_data.vfm )
> {
> - case 0x3c: /* HSM182, HSD172 - 4th gen Core */
> - case 0x3f: /* HSE117 - Xeon E5 v3 */
> - case 0x45: /* HSM182 - 4th gen Core */
> - case 0x46: /* HSM182, HSD172 - 4th gen Core (GT3) */
> - case 0x3d: /* BDM127 - 5th gen Core */
> - case 0x47: /* BDD117 - 5th gen Core (GT3)
> - BDW117 - Xeon E3-1200 v4 */
> - case 0x4f: /* BDF85 - Xeon E5-2600 v4
> - BDH75 - Core-i7 for LGA2011-v3 Socket
> - BDX88 - Xeon E7-x800 v4 */
> - case 0x56: /* BDE105 - Xeon D-1500 */
> + case INTEL_HASWELL:
> + case INTEL_HASWELL_X:
> + case INTEL_HASWELL_L:
> + case INTEL_HASWELL_G:
> + case INTEL_BROADWELL:
> + case INTEL_BROADWELL_G:
> + case INTEL_BROADWELL_X:
> + case INTEL_BROADWELL_D:
> break;
I think it would be nice for the errata numbers to not be lost.
> @@ -3476,19 +3477,16 @@ static void __init ler_to_fixup_check(void)
> * that are not equal to bit[47]. Attempting to context switch this value
> * may cause a #GP. Software should sign extend the MSR.
> */
> - if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
> - boot_cpu_data.x86 != 6 )
> + if ( boot_cpu_data.vendor != X86_VENDOR_INTEL ||
> + boot_cpu_data.family != 6 )
> return;
>
> - switch ( boot_cpu_data.x86_model )
> + switch ( boot_cpu_data.vfm )
> {
> - case 0x3d: /* BDM131 - 5th gen Core */
> - case 0x47: /* BDD??? - 5th gen Core (H-Processor line)
> - BDW120 - Xeon E3-1200 v4 */
> - case 0x4f: /* BDF93 - Xeon E5-2600 v4
> - BDH80 - Core-i7 for LGA2011-v3 Socket
> - BDX93 - Xeon E7-x800 v4 */
> - case 0x56: /* BDE??? - Xeon D-1500 */
> + case INTEL_BROADWELL:
> + case INTEL_BROADWELL_G:
> + case INTEL_BROADWELL_X:
> + case INTEL_BROADWELL_D:
> ler_to_fixup_needed = true;
> break;
> }
Same here then.
Jan
On 10/03/2026 10:26 am, Jan Beulich wrote:
> On 04.03.2026 20:53, Kevin Lampis wrote:
>> struct cpuinfo_x86
>> .x86 => .family
>> .x86_vendor => .vendor
>> .x86_model => .model
>> .x86_mask => .stepping
>>
>> No functional change.
>>
>> This work is part of making Xen safe for Intel family 18/19.
>>
>> Signed-off-by: Kevin Lampis <kevin.lampis@citrix.com>
>> ---
>> I couldn't find any information about these Intel family 6 processors:
>> model 0x5d: /* SoFIA 3G Granite/ES2.1 */
>> model 0x65: /* SoFIA LTE AOSP */
>> model 0x6e: /* Cougar Mountain */
>> Should I add them to intel-family.h?
> We should keep that in sync with Linux, I think, so "no" unless you mean to
> first have respective entries added there.
>
> 0x5d is listed in the SDM, so I'd recommend keeping the entries (using IFM()
> directly for the time being).
>
> 0x65 and 0x6e aren't listed in the SDM, so may never really have hit the
> public. Respective cases can perhaps be dropped, but such dropping would
> again likely better be done in a separate change.
These are the 5G basestations I mentioned during the x86 meeting. Linux
has declined to take take these models into intel-family.h because
they're not general purpose.
I suggest we drop them, including 0x5d. I can do a separate patch.
>
>> @@ -3073,71 +3077,71 @@ static bool __init has_if_pschange_mc(void)
>> * IF_PSCHANGE_MC is only known to affect Intel Family 6 processors at
>> * this time.
>> */
>> - if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
>> - boot_cpu_data.x86 != 6 )
>> + if ( boot_cpu_data.vendor != X86_VENDOR_INTEL ||
>> + boot_cpu_data.family != 6 )
>> return false;
>>
>> - switch ( boot_cpu_data.x86_model )
>> + switch ( boot_cpu_data.vfm )
>> {
>> /*
>> * Core processors since at least Nehalem are vulnerable.
>> */
>> - case 0x1f: /* Auburndale / Havendale */
>> - case 0x1e: /* Nehalem */
>> - case 0x1a: /* Nehalem EP */
>> - case 0x2e: /* Nehalem EX */
>> - case 0x25: /* Westmere */
>> - case 0x2c: /* Westmere EP */
>> - case 0x2f: /* Westmere EX */
>> - case 0x2a: /* SandyBridge */
>> - case 0x2d: /* SandyBridge EP/EX */
>> - case 0x3a: /* IvyBridge */
>> - case 0x3e: /* IvyBridge EP/EX */
>> - case 0x3c: /* Haswell */
>> - case 0x3f: /* Haswell EX/EP */
>> - case 0x45: /* Haswell D */
>> - case 0x46: /* Haswell H */
>> - case 0x3d: /* Broadwell */
>> - case 0x47: /* Broadwell H */
>> - case 0x4f: /* Broadwell EP/EX */
>> - case 0x56: /* Broadwell D */
>> - case 0x4e: /* Skylake M */
>> - case 0x5e: /* Skylake D */
>> - case 0x55: /* Skylake-X / Cascade Lake */
>> - case 0x7d: /* Ice Lake */
>> - case 0x7e: /* Ice Lake */
>> - case 0x8e: /* Kaby / Coffee / Whiskey Lake M */
>> - case 0x9e: /* Kaby / Coffee / Whiskey Lake D */
>> - case 0xa5: /* Comet Lake H/S */
>> - case 0xa6: /* Comet Lake U */
>> + case INTEL_NEHALEM_G:
>> + case INTEL_NEHALEM:
>> + case INTEL_NEHALEM_EP:
>> + case INTEL_NEHALEM_EX:
>> + case INTEL_WESTMERE:
>> + case INTEL_WESTMERE_EP:
>> + case INTEL_WESTMERE_EX:
>> + case INTEL_SANDYBRIDGE:
>> + case INTEL_SANDYBRIDGE_X:
>> + case INTEL_IVYBRIDGE:
>> + case INTEL_IVYBRIDGE_X:
>> + case INTEL_HASWELL:
>> + case INTEL_HASWELL_X:
>> + case INTEL_HASWELL_L:
>> + case INTEL_HASWELL_G:
>> + case INTEL_BROADWELL:
>> + case INTEL_BROADWELL_G:
>> + case INTEL_BROADWELL_X:
>> + case INTEL_BROADWELL_D:
>> + case INTEL_SKYLAKE_L:
>> + case INTEL_SKYLAKE:
>> + case INTEL_SKYLAKE_X:
>> + case INTEL_ICELAKE:
>> + case INTEL_ICELAKE_L:
>> + case INTEL_KABYLAKE_L:
>> + case INTEL_KABYLAKE:
>> + case INTEL_COMETLAKE:
>> + case INTEL_COMETLAKE_L:
>> return true;
>>
>> /*
>> * Atom processors are not vulnerable.
>> */
>> - case 0x1c: /* Pineview */
>> - case 0x26: /* Lincroft */
>> - case 0x27: /* Penwell */
>> - case 0x35: /* Cloverview */
>> - case 0x36: /* Cedarview */
>> - case 0x37: /* Baytrail / Valleyview (Silvermont) */
>> - case 0x4d: /* Avaton / Rangely (Silvermont) */
>> - case 0x4c: /* Cherrytrail / Brasswell */
>> - case 0x4a: /* Merrifield */
>> - case 0x5a: /* Moorefield */
>> - case 0x5c: /* Goldmont */
>> - case 0x5d: /* SoFIA 3G Granite/ES2.1 */
>> - case 0x65: /* SoFIA LTE AOSP */
>> - case 0x5f: /* Denverton */
>> - case 0x6e: /* Cougar Mountain */
>> - case 0x75: /* Lightning Mountain */
>> - case 0x7a: /* Gemini Lake */
>> - case 0x86: /* Jacobsville */
>> + case INTEL_ATOM_BONNELL:
>> + case INTEL_ATOM_BONNELL_MID:
>> + case INTEL_ATOM_SALTWELL_MID:
>> + case INTEL_ATOM_SALTWELL_TABLET:
>> + case INTEL_ATOM_SALTWELL:
>> + case INTEL_ATOM_SILVERMONT:
>> + case INTEL_ATOM_SILVERMONT_D:
>> + case INTEL_ATOM_AIRMONT:
>> + case INTEL_ATOM_SILVERMONT_MID:
>> + case INTEL_ATOM_SILVERMONT_MID2:
> Can the Silvermonts please be grouped together?
>
>> + case INTEL_ATOM_GOLDMONT:
>> + //case 0x5d: /* SoFIA 3G Granite/ES2.1 */ // XXX ???
>> + //case 0x65: /* SoFIA LTE AOSP */ // XXX ???
>> + case INTEL_ATOM_GOLDMONT_D:
>> + //case 0x6e: /* Cougar Mountain */ // XXX ???
>> + case INTEL_ATOM_AIRMONT_NP:
> Same for the Airmonts and ...
>
>> + case INTEL_ATOM_GOLDMONT_PLUS:
> ... the Goldmonts.
We need another sync to intel-family.h. Christian made a correction or
two in this area. I'll do a patch.
~Andrew
On 10.03.2026 16:29, Andrew Cooper wrote: > On 10/03/2026 10:26 am, Jan Beulich wrote: >> On 04.03.2026 20:53, Kevin Lampis wrote: >>> struct cpuinfo_x86 >>> .x86 => .family >>> .x86_vendor => .vendor >>> .x86_model => .model >>> .x86_mask => .stepping >>> >>> No functional change. >>> >>> This work is part of making Xen safe for Intel family 18/19. >>> >>> Signed-off-by: Kevin Lampis <kevin.lampis@citrix.com> >>> --- >>> I couldn't find any information about these Intel family 6 processors: >>> model 0x5d: /* SoFIA 3G Granite/ES2.1 */ >>> model 0x65: /* SoFIA LTE AOSP */ >>> model 0x6e: /* Cougar Mountain */ >>> Should I add them to intel-family.h? >> We should keep that in sync with Linux, I think, so "no" unless you mean to >> first have respective entries added there. >> >> 0x5d is listed in the SDM, so I'd recommend keeping the entries (using IFM() >> directly for the time being). >> >> 0x65 and 0x6e aren't listed in the SDM, so may never really have hit the >> public. Respective cases can perhaps be dropped, but such dropping would >> again likely better be done in a separate change. > > These are the 5G basestations I mentioned during the x86 meeting. Linux > has declined to take take these models into intel-family.h because > they're not general purpose. > > I suggest we drop them, including 0x5d. I can do a separate patch. For 0x5d it's not quite clear what the justification would be. Looking at the SDM, those X3-C3000 don't look any more or less general purpose as C2000 and C1000. I guess I'll learn once you've sent the patch. Jan
On 10/03/2026 3:29 pm, Andrew Cooper wrote:
>>> @@ -3073,71 +3077,71 @@ static bool __init has_if_pschange_mc(void)
>>> * IF_PSCHANGE_MC is only known to affect Intel Family 6 processors at
>>> * this time.
>>> */
>>> - if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
>>> - boot_cpu_data.x86 != 6 )
>>> + if ( boot_cpu_data.vendor != X86_VENDOR_INTEL ||
>>> + boot_cpu_data.family != 6 )
>>> return false;
>>>
>>> - switch ( boot_cpu_data.x86_model )
>>> + switch ( boot_cpu_data.vfm )
>>> {
>>> /*
>>> * Core processors since at least Nehalem are vulnerable.
>>> */
>>> - case 0x1f: /* Auburndale / Havendale */
>>> - case 0x1e: /* Nehalem */
>>> - case 0x1a: /* Nehalem EP */
>>> - case 0x2e: /* Nehalem EX */
>>> - case 0x25: /* Westmere */
>>> - case 0x2c: /* Westmere EP */
>>> - case 0x2f: /* Westmere EX */
>>> - case 0x2a: /* SandyBridge */
>>> - case 0x2d: /* SandyBridge EP/EX */
>>> - case 0x3a: /* IvyBridge */
>>> - case 0x3e: /* IvyBridge EP/EX */
>>> - case 0x3c: /* Haswell */
>>> - case 0x3f: /* Haswell EX/EP */
>>> - case 0x45: /* Haswell D */
>>> - case 0x46: /* Haswell H */
>>> - case 0x3d: /* Broadwell */
>>> - case 0x47: /* Broadwell H */
>>> - case 0x4f: /* Broadwell EP/EX */
>>> - case 0x56: /* Broadwell D */
>>> - case 0x4e: /* Skylake M */
>>> - case 0x5e: /* Skylake D */
>>> - case 0x55: /* Skylake-X / Cascade Lake */
>>> - case 0x7d: /* Ice Lake */
>>> - case 0x7e: /* Ice Lake */
>>> - case 0x8e: /* Kaby / Coffee / Whiskey Lake M */
>>> - case 0x9e: /* Kaby / Coffee / Whiskey Lake D */
>>> - case 0xa5: /* Comet Lake H/S */
>>> - case 0xa6: /* Comet Lake U */
>>> + case INTEL_NEHALEM_G:
>>> + case INTEL_NEHALEM:
>>> + case INTEL_NEHALEM_EP:
>>> + case INTEL_NEHALEM_EX:
>>> + case INTEL_WESTMERE:
>>> + case INTEL_WESTMERE_EP:
>>> + case INTEL_WESTMERE_EX:
>>> + case INTEL_SANDYBRIDGE:
>>> + case INTEL_SANDYBRIDGE_X:
>>> + case INTEL_IVYBRIDGE:
>>> + case INTEL_IVYBRIDGE_X:
>>> + case INTEL_HASWELL:
>>> + case INTEL_HASWELL_X:
>>> + case INTEL_HASWELL_L:
>>> + case INTEL_HASWELL_G:
>>> + case INTEL_BROADWELL:
>>> + case INTEL_BROADWELL_G:
>>> + case INTEL_BROADWELL_X:
>>> + case INTEL_BROADWELL_D:
>>> + case INTEL_SKYLAKE_L:
>>> + case INTEL_SKYLAKE:
>>> + case INTEL_SKYLAKE_X:
>>> + case INTEL_ICELAKE:
>>> + case INTEL_ICELAKE_L:
>>> + case INTEL_KABYLAKE_L:
>>> + case INTEL_KABYLAKE:
>>> + case INTEL_COMETLAKE:
>>> + case INTEL_COMETLAKE_L:
>>> return true;
>>>
>>> /*
>>> * Atom processors are not vulnerable.
>>> */
>>> - case 0x1c: /* Pineview */
>>> - case 0x26: /* Lincroft */
>>> - case 0x27: /* Penwell */
>>> - case 0x35: /* Cloverview */
>>> - case 0x36: /* Cedarview */
>>> - case 0x37: /* Baytrail / Valleyview (Silvermont) */
>>> - case 0x4d: /* Avaton / Rangely (Silvermont) */
>>> - case 0x4c: /* Cherrytrail / Brasswell */
>>> - case 0x4a: /* Merrifield */
>>> - case 0x5a: /* Moorefield */
>>> - case 0x5c: /* Goldmont */
>>> - case 0x5d: /* SoFIA 3G Granite/ES2.1 */
>>> - case 0x65: /* SoFIA LTE AOSP */
>>> - case 0x5f: /* Denverton */
>>> - case 0x6e: /* Cougar Mountain */
>>> - case 0x75: /* Lightning Mountain */
>>> - case 0x7a: /* Gemini Lake */
>>> - case 0x86: /* Jacobsville */
>>> + case INTEL_ATOM_BONNELL:
>>> + case INTEL_ATOM_BONNELL_MID:
>>> + case INTEL_ATOM_SALTWELL_MID:
>>> + case INTEL_ATOM_SALTWELL_TABLET:
>>> + case INTEL_ATOM_SALTWELL:
>>> + case INTEL_ATOM_SILVERMONT:
>>> + case INTEL_ATOM_SILVERMONT_D:
>>> + case INTEL_ATOM_AIRMONT:
>>> + case INTEL_ATOM_SILVERMONT_MID:
>>> + case INTEL_ATOM_SILVERMONT_MID2:
>> Can the Silvermonts please be grouped together?
>>
>>> + case INTEL_ATOM_GOLDMONT:
>>> + //case 0x5d: /* SoFIA 3G Granite/ES2.1 */ // XXX ???
>>> + //case 0x65: /* SoFIA LTE AOSP */ // XXX ???
>>> + case INTEL_ATOM_GOLDMONT_D:
>>> + //case 0x6e: /* Cougar Mountain */ // XXX ???
>>> + case INTEL_ATOM_AIRMONT_NP:
>> Same for the Airmonts and ...
>>
>>> + case INTEL_ATOM_GOLDMONT_PLUS:
>> ... the Goldmonts.
> We need another sync to intel-family.h. Christian made a correction or
> two in this area. I'll do a patch.
Scratch this. It looks like we're already up to date.
~Andrew
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