From: Denis Mukhin <dmukhin@ford.com>
Add emulation logic for FCR register.
Note, that does not hook FIFO interrupt moderation to the FIFO management
code for simplicity.
Signed-off-by: Denis Mukhin <dmukhin@ford.com>
---
Changes since v5:
- fixed UART_FCR_CLRX and UART_FCR_CLTX handling
- Link to v5: https://lore.kernel.org/xen-devel/20250828235409.2835815-8-dmukhin@ford.com/
---
xen/common/emul/vuart/ns16x50.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
index 987d4c06e23b..3fc1112709df 100644
--- a/xen/common/emul/vuart/ns16x50.c
+++ b/xen/common/emul/vuart/ns16x50.c
@@ -372,6 +372,36 @@ static int ns16x50_io_write8(
regs[UART_IER] = val & UART_IER_MASK;
break;
+ case UART_FCR: /* WO */
+ if ( val & UART_FCR_RESERVED0 )
+ ns16x50_warn(vdev, "FCR: attempt to set reserved bit: %x\n",
+ UART_FCR_RESERVED0);
+
+ if ( val & UART_FCR_RESERVED1 )
+ ns16x50_warn(vdev, "FCR: attempt to set reserved bit: %x\n",
+ UART_FCR_RESERVED1);
+
+ if ( val & UART_FCR_CLRX )
+ {
+ ns16x50_fifo_rx_reset(vdev);
+ regs[UART_LSR] &= ~UART_LSR_DR;
+ }
+
+ if ( val & UART_FCR_CLTX )
+ {
+ ns16x50_fifo_tx_reset(vdev);
+ regs[NS16X50_REGS_NUM + UART_IIR] |= UART_IIR_THR;
+ }
+
+ if ( val & UART_FCR_ENABLE )
+ val &= UART_FCR_ENABLE | UART_FCR_DMA | UART_FCR_TRG_MASK;
+ else
+ val = 0;
+
+ regs[UART_FCR] = val;
+
+ break;
+
case UART_LCR:
regs[UART_LCR] = val;
break;
--
2.51.0