The TSC functionality is only related to MSRs by write_tsc(), and this really
does not want to be available as widely as is currently is.
asm/time.h shouldn't be including asm/msr.h, but this turns out to be
sufficiently tangled that I've chosen to break it out into it's own patch.
No functional change.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Jan Beulich <JBeulich@suse.com>
CC: Roger Pau Monné <roger.pau@citrix.com>
---
xen/arch/x86/include/asm/msr.h | 39 ----------------------------
xen/arch/x86/include/asm/time.h | 1 +
xen/arch/x86/include/asm/tsc.h | 46 +++++++++++++++++++++++++++++++++
3 files changed, 47 insertions(+), 39 deletions(-)
create mode 100644 xen/arch/x86/include/asm/tsc.h
diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h
index 4a35cd0fdff6..1c0e768d9123 100644
--- a/xen/arch/x86/include/asm/msr.h
+++ b/xen/arch/x86/include/asm/msr.h
@@ -124,45 +124,6 @@ static inline void msr_split(struct cpu_user_regs *regs, uint64_t val)
regs->rax = (uint32_t)val;
}
-static inline uint64_t rdtsc(void)
-{
- uint64_t low, high;
-
- __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high));
-
- return (high << 32) | low;
-}
-
-static inline uint64_t rdtsc_ordered(void)
-{
- uint64_t low, high, aux;
-
- /*
- * The RDTSC instruction is not serializing. Make it dispatch serializing
- * for the purposes here by issuing LFENCE (or MFENCE if necessary) ahead
- * of it.
- *
- * RDTSCP, otoh, "does wait until all previous instructions have executed
- * and all previous loads are globally visible" (SDM) / "forces all older
- * instructions to retire before reading the timestamp counter" (APM).
- */
- alternative_io_2("lfence; rdtsc",
- "mfence; rdtsc", X86_FEATURE_MFENCE_RDTSC,
- "rdtscp", X86_FEATURE_RDTSCP,
- ASM_OUTPUT2("=a" (low), "=d" (high), "=c" (aux)),
- /* no inputs */);
-
- return (high << 32) | low;
-}
-
-#define __write_tsc(val) wrmsrl(MSR_IA32_TSC, val)
-#define write_tsc(val) ({ \
- /* Reliable TSCs are in lockstep across all CPUs. We should \
- * never write to them. */ \
- ASSERT(!boot_cpu_has(X86_FEATURE_TSC_RELIABLE)); \
- __write_tsc(val); \
-})
-
#define rdpmc(counter,low,high) \
__asm__ __volatile__("rdpmc" \
: "=a" (low), "=d" (high) \
diff --git a/xen/arch/x86/include/asm/time.h b/xen/arch/x86/include/asm/time.h
index 3dfbb5297a25..c55b69831448 100644
--- a/xen/arch/x86/include/asm/time.h
+++ b/xen/arch/x86/include/asm/time.h
@@ -3,6 +3,7 @@
#define __X86_TIME_H__
#include <asm/msr.h>
+#include <asm/tsc.h>
typedef u64 cycles_t;
diff --git a/xen/arch/x86/include/asm/tsc.h b/xen/arch/x86/include/asm/tsc.h
new file mode 100644
index 000000000000..5f48fed26c23
--- /dev/null
+++ b/xen/arch/x86/include/asm/tsc.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef X86_TSC_H
+#define X86_TSC_H
+
+#include <asm/alternative.h>
+
+static inline uint64_t rdtsc(void)
+{
+ uint64_t low, high;
+
+ asm volatile ( "rdtsc" : "=a" (low), "=d" (high) );
+
+ return (high << 32) | low;
+}
+
+static inline uint64_t rdtsc_ordered(void)
+{
+ uint64_t low, high, aux;
+
+ /*
+ * The RDTSC instruction is not serializing. Make it dispatch serializing
+ * for the purposes here by issuing LFENCE (or MFENCE if necessary) ahead
+ * of it.
+ *
+ * RDTSCP, otoh, "does wait until all previous instructions have executed
+ * and all previous loads are globally visible" (SDM) / "forces all older
+ * instructions to retire before reading the timestamp counter" (APM).
+ */
+ alternative_io_2("lfence; rdtsc",
+ "mfence; rdtsc", X86_FEATURE_MFENCE_RDTSC,
+ "rdtscp", X86_FEATURE_RDTSCP,
+ ASM_OUTPUT2("=a" (low), "=d" (high), "=c" (aux)),
+ /* no inputs */);
+
+ return (high << 32) | low;
+}
+
+#define __write_tsc(val) wrmsrl(MSR_IA32_TSC, val)
+#define write_tsc(val) ({ \
+ /* Reliable TSCs are in lockstep across all CPUs. We should \
+ * never write to them. */ \
+ ASSERT(!boot_cpu_has(X86_FEATURE_TSC_RELIABLE)); \
+ __write_tsc(val); \
+})
+
+#endif /* X86_TSC_H */
--
2.39.5
On 15.08.2025 22:41, Andrew Cooper wrote:
> The TSC functionality is only related to MSRs by write_tsc(), and this really
> does not want to be available as widely as is currently is.
>
> asm/time.h shouldn't be including asm/msr.h, but this turns out to be
> sufficiently tangled that I've chosen to break it out into it's own patch.
>
> No functional change.
>
> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
with one nit:
> --- /dev/null
> +++ b/xen/arch/x86/include/asm/tsc.h
> @@ -0,0 +1,46 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +#ifndef X86_TSC_H
> +#define X86_TSC_H
> +
> +#include <asm/alternative.h>
> +
> +static inline uint64_t rdtsc(void)
> +{
> + uint64_t low, high;
> +
> + asm volatile ( "rdtsc" : "=a" (low), "=d" (high) );
> +
> + return (high << 32) | low;
> +}
> +
> +static inline uint64_t rdtsc_ordered(void)
> +{
> + uint64_t low, high, aux;
> +
> + /*
> + * The RDTSC instruction is not serializing. Make it dispatch serializing
> + * for the purposes here by issuing LFENCE (or MFENCE if necessary) ahead
> + * of it.
> + *
> + * RDTSCP, otoh, "does wait until all previous instructions have executed
> + * and all previous loads are globally visible" (SDM) / "forces all older
> + * instructions to retire before reading the timestamp counter" (APM).
> + */
> + alternative_io_2("lfence; rdtsc",
> + "mfence; rdtsc", X86_FEATURE_MFENCE_RDTSC,
> + "rdtscp", X86_FEATURE_RDTSCP,
> + ASM_OUTPUT2("=a" (low), "=d" (high), "=c" (aux)),
> + /* no inputs */);
> +
> + return (high << 32) | low;
> +}
> +
> +#define __write_tsc(val) wrmsrl(MSR_IA32_TSC, val)
> +#define write_tsc(val) ({ \
> + /* Reliable TSCs are in lockstep across all CPUs. We should \
> + * never write to them. */ \
This comment may want to become a proper Xen-style one while being moved.
Jan
On Mon, Aug 18, 2025 at 2:07 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 15.08.2025 22:41, Andrew Cooper wrote:
> > The TSC functionality is only related to MSRs by write_tsc(), and this really
> > does not want to be available as widely as is currently is.
> >
> > asm/time.h shouldn't be including asm/msr.h, but this turns out to be
> > sufficiently tangled that I've chosen to break it out into it's own patch.
> >
> > No functional change.
> >
> > Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
>
> Acked-by: Jan Beulich <jbeulich@suse.com>
> with one nit:
>
> > --- /dev/null
> > +++ b/xen/arch/x86/include/asm/tsc.h
> > @@ -0,0 +1,46 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +#ifndef X86_TSC_H
> > +#define X86_TSC_H
> > +
> > +#include <asm/alternative.h>
> > +
> > +static inline uint64_t rdtsc(void)
> > +{
> > + uint64_t low, high;
> > +
> > + asm volatile ( "rdtsc" : "=a" (low), "=d" (high) );
> > +
> > + return (high << 32) | low;
> > +}
> > +
> > +static inline uint64_t rdtsc_ordered(void)
> > +{
> > + uint64_t low, high, aux;
> > +
> > + /*
> > + * The RDTSC instruction is not serializing. Make it dispatch serializing
> > + * for the purposes here by issuing LFENCE (or MFENCE if necessary) ahead
> > + * of it.
> > + *
> > + * RDTSCP, otoh, "does wait until all previous instructions have executed
> > + * and all previous loads are globally visible" (SDM) / "forces all older
> > + * instructions to retire before reading the timestamp counter" (APM).
> > + */
> > + alternative_io_2("lfence; rdtsc",
> > + "mfence; rdtsc", X86_FEATURE_MFENCE_RDTSC,
> > + "rdtscp", X86_FEATURE_RDTSCP,
> > + ASM_OUTPUT2("=a" (low), "=d" (high), "=c" (aux)),
> > + /* no inputs */);
> > +
> > + return (high << 32) | low;
> > +}
> > +
> > +#define __write_tsc(val) wrmsrl(MSR_IA32_TSC, val)
> > +#define write_tsc(val) ({ \
> > + /* Reliable TSCs are in lockstep across all CPUs. We should \
> > + * never write to them. */ \
>
> This comment may want to become a proper Xen-style one while being moved.
>
> Jan
>
Does it make sense to move the comment out of the macro?
Frediano
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