NEHALEM_EX is affected by the erratum too.

Change the comment to be the full text, rather than interpretation of it.

Fixes: 95807bcae47e ("C6 state with EOI issue fix for some Intel processors")
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Jan Beulich <JBeulich@suse.com>
CC: Roger Pau Monné <roger.pau@citrix.com>

Pulled out of the cleanup series as it wants backporting.
---
 xen/arch/x86/acpi/cpu_idle.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index 19f710f0dd9d..f422316b03e2 100644
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -584,18 +584,24 @@ bool errata_c6_workaround(void)
     {
 #define INTEL_FAM6_MODEL(m) { X86_VENDOR_INTEL, 6, m, X86_FEATURE_ALWAYS }
         /*
-         * Errata AAJ72: EOI Transaction May Not be Sent if Software Enters
-         * Core C6 During an Interrupt Service Routine"
+         * Errata AAJ72/etc: EOI Transaction May Not be Sent if Software
+         * Enters Core C6 During an Interrupt Service Routine
          *
-         * There was an errata with some Core i7 processors that an EOI
-         * transaction may not be sent if software enters core C6 during an
-         * interrupt service routine. So we don't enter deep Cx state if
-         * there is an EOI pending.
+         * If core C6 is entered after the start of an interrupt service
+         * routine but before a write to the APIC EOI (End of Interrupt)
+         * register, and the core is woken up by an event other than a fixed
+         * interrupt source the core may drop the EOI transaction the next
+         * time APIC EOI register is written and further interrupts from the
+         * same or lower priority level will be blocked.
+         *
+         * Software should check the ISR register and if any interrupts are in
+	 * service only enter C1.
          */
         static const struct x86_cpu_id eoi_errata[] = {
-            INTEL_FAM6_MODEL(0x1a),
+            INTEL_FAM6_MODEL(0x1a), /* AAJ72 */
             INTEL_FAM6_MODEL(0x1e),
             INTEL_FAM6_MODEL(0x1f),
+            INTEL_FAM6_MODEL(0x2e), /* BA106 */
             INTEL_FAM6_MODEL(0x25),
             INTEL_FAM6_MODEL(0x2c),
             INTEL_FAM6_MODEL(0x2f),
-- 
2.39.5

On 17.07.2025 18:28, Andrew Cooper wrote:
> NEHALEM_EX is affected by the erratum too.
> 
> Change the comment to be the full text, rather than interpretation of it.
> 
> Fixes: 95807bcae47e ("C6 state with EOI issue fix for some Intel processors")
> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>

Reviewed-by: Jan Beulich <jbeulich@suse.com>
(maybe also a weak Reported-by:?) with (nit) ...

> --- a/xen/arch/x86/acpi/cpu_idle.c
> +++ b/xen/arch/x86/acpi/cpu_idle.c
> @@ -584,18 +584,24 @@ bool errata_c6_workaround(void)
>      {
>  #define INTEL_FAM6_MODEL(m) { X86_VENDOR_INTEL, 6, m, X86_FEATURE_ALWAYS }
>          /*
> -         * Errata AAJ72: EOI Transaction May Not be Sent if Software Enters
> -         * Core C6 During an Interrupt Service Routine"
> +         * Errata AAJ72/etc: EOI Transaction May Not be Sent if Software
> +         * Enters Core C6 During an Interrupt Service Routine
>           *
> -         * There was an errata with some Core i7 processors that an EOI
> -         * transaction may not be sent if software enters core C6 during an
> -         * interrupt service routine. So we don't enter deep Cx state if
> -         * there is an EOI pending.
> +         * If core C6 is entered after the start of an interrupt service
> +         * routine but before a write to the APIC EOI (End of Interrupt)
> +         * register, and the core is woken up by an event other than a fixed
> +         * interrupt source the core may drop the EOI transaction the next
> +         * time APIC EOI register is written and further interrupts from the
> +         * same or lower priority level will be blocked.
> +         *
> +         * Software should check the ISR register and if any interrupts are in
> +	 * service only enter C1.

... the indentation issue here corrected.

Jan