Define prepare_selector(), read_protection_region() and
write_protection_region() for arm32. Also, define
GENERATE_{READ/WRITE}_PR_REG_OTHERS to access MPU regions from 32 to 254.
Enable pr_{get/set}_{base/limit}(), region_is_valid() for arm32.
Enable pr_of_addr() for arm32.
The maximum number of regions supported is 255 (which corresponds to the
maximum value in HMPUIR).
Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
---
Changes from :-
v1 - 1. Enable write_protection_region() for aarch32.
v2 - 1. Enable access to protection regions from 0 - 255.
v3 - 1. The maximum number of regions is 255. Thus, regions numbered 0 - 254
are supported.
2. prepare_selector() is modified to ensure HPRSELR is written when accessing
any region beyond 31 and the current value differs from the region number to
be accessed.
xen/arch/arm/include/asm/mpu.h | 2 -
xen/arch/arm/mpu/Makefile | 1 +
xen/arch/arm/mpu/arm32/Makefile | 1 +
xen/arch/arm/mpu/arm32/mm.c | 164 ++++++++++++++++++++++++++++++++
xen/arch/arm/mpu/mm.c | 2 -
5 files changed, 166 insertions(+), 4 deletions(-)
create mode 100644 xen/arch/arm/mpu/arm32/Makefile
create mode 100644 xen/arch/arm/mpu/arm32/mm.c
diff --git a/xen/arch/arm/include/asm/mpu.h b/xen/arch/arm/include/asm/mpu.h
index 8f06ddac0f..63560c613b 100644
--- a/xen/arch/arm/include/asm/mpu.h
+++ b/xen/arch/arm/include/asm/mpu.h
@@ -25,7 +25,6 @@
#ifndef __ASSEMBLY__
-#ifdef CONFIG_ARM_64
/*
* Set base address of MPU protection region.
*
@@ -85,7 +84,6 @@ static inline bool region_is_valid(const pr_t *pr)
{
return pr->prlar.reg.en;
}
-#endif /* CONFIG_ARM_64 */
#endif /* __ASSEMBLY__ */
diff --git a/xen/arch/arm/mpu/Makefile b/xen/arch/arm/mpu/Makefile
index 5ad15e93be..58c9b5b4e8 100644
--- a/xen/arch/arm/mpu/Makefile
+++ b/xen/arch/arm/mpu/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_ARM_32) += domain-page.o
+obj-$(CONFIG_ARM_32) += arm32/
obj-$(CONFIG_ARM_64) += arm64/
obj-y += mm.o
obj-y += p2m.o
diff --git a/xen/arch/arm/mpu/arm32/Makefile b/xen/arch/arm/mpu/arm32/Makefile
new file mode 100644
index 0000000000..b18cec4836
--- /dev/null
+++ b/xen/arch/arm/mpu/arm32/Makefile
@@ -0,0 +1 @@
+obj-y += mm.o
diff --git a/xen/arch/arm/mpu/arm32/mm.c b/xen/arch/arm/mpu/arm32/mm.c
new file mode 100644
index 0000000000..c0317a4ada
--- /dev/null
+++ b/xen/arch/arm/mpu/arm32/mm.c
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <xen/bug.h>
+#include <xen/types.h>
+#include <asm/mpu.h>
+#include <asm/sysregs.h>
+#include <asm/system.h>
+
+#define GENERATE_WRITE_PR_REG_CASE(num, pr) \
+ case num: \
+ { \
+ WRITE_SYSREG(pr->prbar.bits, HPRBAR##num); \
+ WRITE_SYSREG(pr->prlar.bits, HPRLAR##num); \
+ break; \
+ }
+
+#define GENERATE_WRITE_PR_REG_OTHERS(num, pr) \
+ case num: \
+ { \
+ WRITE_SYSREG(pr->prbar.bits, HPRBAR); \
+ WRITE_SYSREG(pr->prlar.bits, HPRLAR); \
+ break; \
+ }
+
+#define GENERATE_READ_PR_REG_CASE(num, pr) \
+ case num: \
+ { \
+ pr->prbar.bits = READ_SYSREG(HPRBAR##num); \
+ pr->prlar.bits = READ_SYSREG(HPRLAR##num); \
+ break; \
+ }
+
+#define GENERATE_READ_PR_REG_OTHERS(num, pr) \
+ case num: \
+ { \
+ pr->prbar.bits = READ_SYSREG(HPRBAR); \
+ pr->prlar.bits = READ_SYSREG(HPRLAR); \
+ break; \
+ }
+
+/*
+ * Armv8-R supports direct access and indirect access to the MPU regions through
+ * registers:
+ * - indirect access involves changing the MPU region selector, issuing an isb
+ * barrier and accessing the selected region through specific registers
+ * - direct access involves accessing specific registers that point to
+ * specific MPU regions, without changing the selector, avoiding the use of
+ * a barrier.
+ * For Arm32 the HPR{B,L}AR<n> (for n=0..31) are used for direct access to the
+ * first 32 MPU regions.
+ * For MPU region numbered 32..254, one need to set the region number in HPRSELR,
+ * followed by configuring HPR{B,L}AR.
+ */
+static void prepare_selector(uint8_t *sel)
+{
+ uint8_t cur_sel = *sel;
+ /* The top 24 bits of HPRSELR are RES0. */
+ uint8_t val = READ_SYSREG(HPRSELR) & 0xff;
+
+ if ( (cur_sel > 31) && (cur_sel != val) )
+ {
+ WRITE_SYSREG(cur_sel, HPRSELR);
+ isb();
+ }
+}
+
+void read_protection_region(pr_t *pr_read, uint8_t sel)
+{
+ prepare_selector(&sel);
+
+ switch ( sel )
+ {
+ GENERATE_READ_PR_REG_CASE(0, pr_read);
+ GENERATE_READ_PR_REG_CASE(1, pr_read);
+ GENERATE_READ_PR_REG_CASE(2, pr_read);
+ GENERATE_READ_PR_REG_CASE(3, pr_read);
+ GENERATE_READ_PR_REG_CASE(4, pr_read);
+ GENERATE_READ_PR_REG_CASE(5, pr_read);
+ GENERATE_READ_PR_REG_CASE(6, pr_read);
+ GENERATE_READ_PR_REG_CASE(7, pr_read);
+ GENERATE_READ_PR_REG_CASE(8, pr_read);
+ GENERATE_READ_PR_REG_CASE(9, pr_read);
+ GENERATE_READ_PR_REG_CASE(10, pr_read);
+ GENERATE_READ_PR_REG_CASE(11, pr_read);
+ GENERATE_READ_PR_REG_CASE(12, pr_read);
+ GENERATE_READ_PR_REG_CASE(13, pr_read);
+ GENERATE_READ_PR_REG_CASE(14, pr_read);
+ GENERATE_READ_PR_REG_CASE(15, pr_read);
+ GENERATE_READ_PR_REG_CASE(16, pr_read);
+ GENERATE_READ_PR_REG_CASE(17, pr_read);
+ GENERATE_READ_PR_REG_CASE(18, pr_read);
+ GENERATE_READ_PR_REG_CASE(19, pr_read);
+ GENERATE_READ_PR_REG_CASE(20, pr_read);
+ GENERATE_READ_PR_REG_CASE(21, pr_read);
+ GENERATE_READ_PR_REG_CASE(22, pr_read);
+ GENERATE_READ_PR_REG_CASE(23, pr_read);
+ GENERATE_READ_PR_REG_CASE(24, pr_read);
+ GENERATE_READ_PR_REG_CASE(25, pr_read);
+ GENERATE_READ_PR_REG_CASE(26, pr_read);
+ GENERATE_READ_PR_REG_CASE(27, pr_read);
+ GENERATE_READ_PR_REG_CASE(28, pr_read);
+ GENERATE_READ_PR_REG_CASE(29, pr_read);
+ GENERATE_READ_PR_REG_CASE(30, pr_read);
+ GENERATE_READ_PR_REG_CASE(31, pr_read);
+ GENERATE_READ_PR_REG_OTHERS(32 ... 254, pr_read);
+ default:
+ BUG(); /* Can't happen */
+ break;
+ }
+}
+
+void write_protection_region(const pr_t *pr_write, uint8_t sel)
+{
+ prepare_selector(&sel);
+
+ switch ( sel )
+ {
+ GENERATE_WRITE_PR_REG_CASE(0, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(1, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(2, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(3, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(4, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(5, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(6, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(7, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(8, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(9, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(10, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(11, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(12, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(13, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(14, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(15, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(16, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(17, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(18, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(19, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(20, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(21, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(22, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(23, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(24, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(25, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(26, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(27, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(28, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(29, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(30, pr_write);
+ GENERATE_WRITE_PR_REG_CASE(31, pr_write);
+ GENERATE_WRITE_PR_REG_OTHERS(32 ... 254, pr_write);
+ default:
+ BUG(); /* Can't happen */
+ break;
+ }
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c
index 7ab68fc8c7..ccfb37a67b 100644
--- a/xen/arch/arm/mpu/mm.c
+++ b/xen/arch/arm/mpu/mm.c
@@ -39,7 +39,6 @@ static void __init __maybe_unused build_assertions(void)
BUILD_BUG_ON(PAGE_SIZE != SZ_4K);
}
-#ifdef CONFIG_ARM_64
pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned int flags)
{
unsigned int attr_idx = PAGE_AI_MASK(flags);
@@ -110,7 +109,6 @@ pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned int flags)
return region;
}
-#endif /* CONFIG_ARM_64 */
void __init setup_mm(void)
{
--
2.25.1Hi Ayan,
On 17/06/2025 12:12, Ayan Kumar Halder wrote:
> Define prepare_selector(), read_protection_region() and
> write_protection_region() for arm32. Also, define
> GENERATE_{READ/WRITE}_PR_REG_OTHERS to access MPU regions from 32 to 254.
>
> Enable pr_{get/set}_{base/limit}(), region_is_valid() for arm32.
> Enable pr_of_addr() for arm32.
>
> The maximum number of regions supported is 255 (which corresponds to the
> maximum value in HMPUIR).
>
> Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
Acked-by: Julien Grall <jgrall@amazon.com>
Cheers,
> ---
> Changes from :-
>
> v1 - 1. Enable write_protection_region() for aarch32.
>
> v2 - 1. Enable access to protection regions from 0 - 255.
>
> v3 - 1. The maximum number of regions is 255. Thus, regions numbered 0 - 254
> are supported.
>
> 2. prepare_selector() is modified to ensure HPRSELR is written when accessing
> any region beyond 31 and the current value differs from the region number to
> be accessed.
>
> xen/arch/arm/include/asm/mpu.h | 2 -
> xen/arch/arm/mpu/Makefile | 1 +
> xen/arch/arm/mpu/arm32/Makefile | 1 +
> xen/arch/arm/mpu/arm32/mm.c | 164 ++++++++++++++++++++++++++++++++
> xen/arch/arm/mpu/mm.c | 2 -
> 5 files changed, 166 insertions(+), 4 deletions(-)
> create mode 100644 xen/arch/arm/mpu/arm32/Makefile
> create mode 100644 xen/arch/arm/mpu/arm32/mm.c
>
> diff --git a/xen/arch/arm/include/asm/mpu.h b/xen/arch/arm/include/asm/mpu.h
> index 8f06ddac0f..63560c613b 100644
> --- a/xen/arch/arm/include/asm/mpu.h
> +++ b/xen/arch/arm/include/asm/mpu.h
> @@ -25,7 +25,6 @@
>
> #ifndef __ASSEMBLY__
>
> -#ifdef CONFIG_ARM_64
> /*
> * Set base address of MPU protection region.
> *
> @@ -85,7 +84,6 @@ static inline bool region_is_valid(const pr_t *pr)
> {
> return pr->prlar.reg.en;
> }
> -#endif /* CONFIG_ARM_64 */
>
> #endif /* __ASSEMBLY__ */
>
> diff --git a/xen/arch/arm/mpu/Makefile b/xen/arch/arm/mpu/Makefile
> index 5ad15e93be..58c9b5b4e8 100644
> --- a/xen/arch/arm/mpu/Makefile
> +++ b/xen/arch/arm/mpu/Makefile
> @@ -1,4 +1,5 @@
> obj-$(CONFIG_ARM_32) += domain-page.o
> +obj-$(CONFIG_ARM_32) += arm32/
> obj-$(CONFIG_ARM_64) += arm64/
> obj-y += mm.o
> obj-y += p2m.o
> diff --git a/xen/arch/arm/mpu/arm32/Makefile b/xen/arch/arm/mpu/arm32/Makefile
> new file mode 100644
> index 0000000000..b18cec4836
> --- /dev/null
> +++ b/xen/arch/arm/mpu/arm32/Makefile
> @@ -0,0 +1 @@
> +obj-y += mm.o
> diff --git a/xen/arch/arm/mpu/arm32/mm.c b/xen/arch/arm/mpu/arm32/mm.c
> new file mode 100644
> index 0000000000..c0317a4ada
> --- /dev/null
> +++ b/xen/arch/arm/mpu/arm32/mm.c
> @@ -0,0 +1,164 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#include <xen/bug.h>
> +#include <xen/types.h>
> +#include <asm/mpu.h>
> +#include <asm/sysregs.h>
> +#include <asm/system.h>
> +
> +#define GENERATE_WRITE_PR_REG_CASE(num, pr) \
> + case num: \
> + { \
> + WRITE_SYSREG(pr->prbar.bits, HPRBAR##num); \
> + WRITE_SYSREG(pr->prlar.bits, HPRLAR##num); \
> + break; \
> + }
> +
> +#define GENERATE_WRITE_PR_REG_OTHERS(num, pr) \
> + case num: \
> + { \
> + WRITE_SYSREG(pr->prbar.bits, HPRBAR); \
> + WRITE_SYSREG(pr->prlar.bits, HPRLAR); \
> + break; \
> + }
> +
> +#define GENERATE_READ_PR_REG_CASE(num, pr) \
> + case num: \
> + { \
> + pr->prbar.bits = READ_SYSREG(HPRBAR##num); \
> + pr->prlar.bits = READ_SYSREG(HPRLAR##num); \
> + break; \
> + }
> +
> +#define GENERATE_READ_PR_REG_OTHERS(num, pr) \
> + case num: \
> + { \
> + pr->prbar.bits = READ_SYSREG(HPRBAR); \
> + pr->prlar.bits = READ_SYSREG(HPRLAR); \
> + break; \
> + }
> +
> +/*
> + * Armv8-R supports direct access and indirect access to the MPU regions through
> + * registers:
> + * - indirect access involves changing the MPU region selector, issuing an isb
> + * barrier and accessing the selected region through specific registers
> + * - direct access involves accessing specific registers that point to
> + * specific MPU regions, without changing the selector, avoiding the use of
> + * a barrier.
> + * For Arm32 the HPR{B,L}AR<n> (for n=0..31) are used for direct access to the
> + * first 32 MPU regions.
> + * For MPU region numbered 32..254, one need to set the region number in HPRSELR,
> + * followed by configuring HPR{B,L}AR.
> + */
> +static void prepare_selector(uint8_t *sel)
> +{
> + uint8_t cur_sel = *sel;
> + /* The top 24 bits of HPRSELR are RES0. */
> + uint8_t val = READ_SYSREG(HPRSELR) & 0xff;
> +
> + if ( (cur_sel > 31) && (cur_sel != val) )
> + {
> + WRITE_SYSREG(cur_sel, HPRSELR);
> + isb();
> + }
> +}
> +
> +void read_protection_region(pr_t *pr_read, uint8_t sel)
> +{
> + prepare_selector(&sel);
> +
> + switch ( sel )
> + {
> + GENERATE_READ_PR_REG_CASE(0, pr_read);
> + GENERATE_READ_PR_REG_CASE(1, pr_read);
> + GENERATE_READ_PR_REG_CASE(2, pr_read);
> + GENERATE_READ_PR_REG_CASE(3, pr_read);
> + GENERATE_READ_PR_REG_CASE(4, pr_read);
> + GENERATE_READ_PR_REG_CASE(5, pr_read);
> + GENERATE_READ_PR_REG_CASE(6, pr_read);
> + GENERATE_READ_PR_REG_CASE(7, pr_read);
> + GENERATE_READ_PR_REG_CASE(8, pr_read);
> + GENERATE_READ_PR_REG_CASE(9, pr_read);
> + GENERATE_READ_PR_REG_CASE(10, pr_read);
> + GENERATE_READ_PR_REG_CASE(11, pr_read);
> + GENERATE_READ_PR_REG_CASE(12, pr_read);
> + GENERATE_READ_PR_REG_CASE(13, pr_read);
> + GENERATE_READ_PR_REG_CASE(14, pr_read);
> + GENERATE_READ_PR_REG_CASE(15, pr_read);
> + GENERATE_READ_PR_REG_CASE(16, pr_read);
> + GENERATE_READ_PR_REG_CASE(17, pr_read);
> + GENERATE_READ_PR_REG_CASE(18, pr_read);
> + GENERATE_READ_PR_REG_CASE(19, pr_read);
> + GENERATE_READ_PR_REG_CASE(20, pr_read);
> + GENERATE_READ_PR_REG_CASE(21, pr_read);
> + GENERATE_READ_PR_REG_CASE(22, pr_read);
> + GENERATE_READ_PR_REG_CASE(23, pr_read);
> + GENERATE_READ_PR_REG_CASE(24, pr_read);
> + GENERATE_READ_PR_REG_CASE(25, pr_read);
> + GENERATE_READ_PR_REG_CASE(26, pr_read);
> + GENERATE_READ_PR_REG_CASE(27, pr_read);
> + GENERATE_READ_PR_REG_CASE(28, pr_read);
> + GENERATE_READ_PR_REG_CASE(29, pr_read);
> + GENERATE_READ_PR_REG_CASE(30, pr_read);
> + GENERATE_READ_PR_REG_CASE(31, pr_read);
> + GENERATE_READ_PR_REG_OTHERS(32 ... 254, pr_read);
> + default:
> + BUG(); /* Can't happen */
> + break;
> + }
> +}
> +
> +void write_protection_region(const pr_t *pr_write, uint8_t sel)
> +{
> + prepare_selector(&sel);
> +
> + switch ( sel )
> + {
> + GENERATE_WRITE_PR_REG_CASE(0, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(1, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(2, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(3, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(4, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(5, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(6, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(7, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(8, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(9, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(10, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(11, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(12, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(13, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(14, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(15, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(16, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(17, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(18, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(19, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(20, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(21, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(22, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(23, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(24, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(25, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(26, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(27, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(28, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(29, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(30, pr_write);
> + GENERATE_WRITE_PR_REG_CASE(31, pr_write);
> + GENERATE_WRITE_PR_REG_OTHERS(32 ... 254, pr_write);
> + default:
> + BUG(); /* Can't happen */
> + break;
> + }
> +}
> +
> +/*
> + * Local variables:
> + * mode: C
> + * c-file-style: "BSD"
> + * c-basic-offset: 4
> + * indent-tabs-mode: nil
> + * End:
> + */
> diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c
> index 7ab68fc8c7..ccfb37a67b 100644
> --- a/xen/arch/arm/mpu/mm.c
> +++ b/xen/arch/arm/mpu/mm.c
> @@ -39,7 +39,6 @@ static void __init __maybe_unused build_assertions(void)
> BUILD_BUG_ON(PAGE_SIZE != SZ_4K);
> }
>
> -#ifdef CONFIG_ARM_64
> pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned int flags)
> {
> unsigned int attr_idx = PAGE_AI_MASK(flags);
> @@ -110,7 +109,6 @@ pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned int flags)
>
> return region;
> }
> -#endif /* CONFIG_ARM_64 */
>
> void __init setup_mm(void)
> {
--
Julien Grall
Hi Ayan,
> +/*
> + * Armv8-R supports direct access and indirect access to the MPU regions through
> + * registers:
> + * - indirect access involves changing the MPU region selector, issuing an isb
> + * barrier and accessing the selected region through specific registers
> + * - direct access involves accessing specific registers that point to
> + * specific MPU regions, without changing the selector, avoiding the use of
> + * a barrier.
> + * For Arm32 the HPR{B,L}AR<n> (for n=0..31) are used for direct access to the
> + * first 32 MPU regions.
> + * For MPU region numbered 32..254, one need to set the region number in HPRSELR,
> + * followed by configuring HPR{B,L}AR.
> + */
> +static void prepare_selector(uint8_t *sel)
NIT: s/one need/one needs/
NIT: s/MPU region numbered/MPU regions numbered/
Also - it's not clear to me what is meant by "followed by configuring HPR{B,L}AR";
if I understand correctly, once we have set the region number in HPRSELR
and issued an isb we can simply read/write HPR{B,L}AR as indicated in
the bullet point above?
> On Tue, Jun 17, 2025 at 12:12:51PM +0000, Ayan Kumar Halder wrote:
> Define prepare_selector(), read_protection_region() and
> write_protection_region() for arm32. Also, define
> GENERATE_{READ/WRITE}_PR_REG_OTHERS to access MPU regions from 32 to 254.
>
> Enable pr_{get/set}_{base/limit}(), region_is_valid() for arm32.
> Enable pr_of_addr() for arm32.
>
> The maximum number of regions supported is 255 (which corresponds to the
> maximum value in HMPUIR).
>
> Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
> Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
> ---
Apart from the above, all LGTM! I've tested compilation for both 64-bit
and 32-bit and all is building successfully.
Reviewed-by: Hari Limaye <hari.limaye@arm.com>
Tested-by: Hari Limaye <hari.limaye@arm.com>
Cheers,
Hari
On 17/06/2025 16:31, Hari Limaye wrote:
> Hi Ayan,
Hi Hari,
>
>> +/*
>> + * Armv8-R supports direct access and indirect access to the MPU regions through
>> + * registers:
>> + * - indirect access involves changing the MPU region selector, issuing an isb
>> + * barrier and accessing the selected region through specific registers
>> + * - direct access involves accessing specific registers that point to
>> + * specific MPU regions, without changing the selector, avoiding the use of
>> + * a barrier.
>> + * For Arm32 the HPR{B,L}AR<n> (for n=0..31) are used for direct access to the
>> + * first 32 MPU regions.
>> + * For MPU region numbered 32..254, one need to set the region number in HPRSELR,
>> + * followed by configuring HPR{B,L}AR.
>> + */
>> +static void prepare_selector(uint8_t *sel)
> NIT: s/one need/one needs/
> NIT: s/MPU region numbered/MPU regions numbered/
Ack.
>
> Also - it's not clear to me what is meant by "followed by configuring HPR{B,L}AR";
> if I understand correctly, once we have set the region number in HPRSELR
> and issued an isb we can simply read/write HPR{B,L}AR as indicated in
> the bullet point above?
yes, this is correct.
>
>> On Tue, Jun 17, 2025 at 12:12:51PM +0000, Ayan Kumar Halder wrote:
>> Define prepare_selector(), read_protection_region() and
>> write_protection_region() for arm32. Also, define
>> GENERATE_{READ/WRITE}_PR_REG_OTHERS to access MPU regions from 32 to 254.
>>
>> Enable pr_{get/set}_{base/limit}(), region_is_valid() for arm32.
>> Enable pr_of_addr() for arm32.
>>
>> The maximum number of regions supported is 255 (which corresponds to the
>> maximum value in HMPUIR).
>>
>> Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
>> Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
>> ---
> Apart from the above, all LGTM! I've tested compilation for both 64-bit
> and 32-bit and all is building successfully.
>
> Reviewed-by: Hari Limaye <hari.limaye@arm.com>
> Tested-by: Hari Limaye <hari.limaye@arm.com>
- Ayan
Hi Ayan,
> On 17 Jun 2025, at 12:12, Ayan Kumar Halder <ayan.kumar.halder@amd.com> wrote:
>
> Define prepare_selector(), read_protection_region() and
> write_protection_region() for arm32. Also, define
> GENERATE_{READ/WRITE}_PR_REG_OTHERS to access MPU regions from 32 to 254.
>
> Enable pr_{get/set}_{base/limit}(), region_is_valid() for arm32.
> Enable pr_of_addr() for arm32.
>
> The maximum number of regions supported is 255 (which corresponds to the
> maximum value in HMPUIR).
>
> Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
> —
This looks good to me!
Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
Cheers,
Luca
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