regions.inc is added to hold the common earlyboot MPU regions configurations
between arm64 and arm32.
prepare_xen_region, fail_insufficient_regions() will be used by both arm32 and
arm64. Thus, they have been moved to regions.inc.
*_PRBAR are moved to arm64/sysregs.h.
*_PRLAR are moved to regions.inc as they are common between arm32 and arm64.
Introduce WRITE_SYSREG_ASM to write to the system registers from regions.inc.
Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
Tested-by: Luca Fancellu <luca.fancellu@arm.com>
---
Changes from
v1 -
1. enable_mpu() now sets HMAIR{0,1} registers. This is similar to what is
being done in enable_mmu(). All the mm related configurations happen in this
function.
2. Fixed some typos.
v2 -
1. Extracted the arm64 head.S functions/macros in a common file.
v3 -
1. Moved *_PRLAR are moved to prepare_xen_region.inc
2. enable_boot_cpu_mm() is preserved in mpu/head.S.
3. STORE_SYSREG is renamed as WRITE_SYSREG_ASM()
4. LOAD_SYSREG is removed.
5. No need to save/restore lr in enable_boot_cpu_mm(). IOW, keep it as it was
in the original code.
v4 -
1. Rename prepare_xen_region.inc to common.inc
2. enable_secondary_cpu_mm() is moved back to mpu/head.S.
v5 -
1. Rename common.inc to regions.inc.
2. WRITE_SYSREG_ASM() in enclosed within #ifdef __ASSEMBLY__.
v6 -
1. Add Michal's R-b and Luca's T-b.
xen/arch/arm/arm64/mpu/head.S | 78 +----------------------
xen/arch/arm/include/asm/arm64/sysregs.h | 13 ++++
xen/arch/arm/include/asm/mpu/regions.inc | 79 ++++++++++++++++++++++++
3 files changed, 93 insertions(+), 77 deletions(-)
create mode 100644 xen/arch/arm/include/asm/mpu/regions.inc
diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S
index ed01993d85..6d336cafbb 100644
--- a/xen/arch/arm/arm64/mpu/head.S
+++ b/xen/arch/arm/arm64/mpu/head.S
@@ -3,83 +3,7 @@
* Start-of-day code for an Armv8-R MPU system.
*/
-#include <asm/early_printk.h>
-#include <asm/mpu.h>
-
-/* Backgroud region enable/disable */
-#define SCTLR_ELx_BR BIT(17, UL)
-
-#define REGION_TEXT_PRBAR 0x38 /* SH=11 AP=10 XN=00 */
-#define REGION_RO_PRBAR 0x3A /* SH=11 AP=10 XN=10 */
-#define REGION_DATA_PRBAR 0x32 /* SH=11 AP=00 XN=10 */
-#define REGION_DEVICE_PRBAR 0x22 /* SH=10 AP=00 XN=10 */
-
-#define REGION_NORMAL_PRLAR 0x0f /* NS=0 ATTR=111 EN=1 */
-#define REGION_DEVICE_PRLAR 0x09 /* NS=0 ATTR=100 EN=1 */
-
-/*
- * Macro to prepare and set a EL2 MPU memory region.
- * We will also create an according MPU memory region entry, which
- * is a structure of pr_t, in table \prmap.
- *
- * sel: region selector
- * base: reg storing base address
- * limit: reg storing limit address
- * prbar: store computed PRBAR_EL2 value
- * prlar: store computed PRLAR_EL2 value
- * maxcount: maximum number of EL2 regions supported
- * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it will be
- * REGION_DATA_PRBAR
- * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it will be
- * REGION_NORMAL_PRLAR
- *
- * Preserves \maxcount
- * Output:
- * \sel: Next available region selector index.
- * Clobbers \base, \limit, \prbar, \prlar
- *
- * Note that all parameters using registers should be distinct.
- */
-.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_prbar=REGION_DATA_PRBAR, attr_prlar=REGION_NORMAL_PRLAR
- /* Check if the region is empty */
- cmp \base, \limit
- beq 1f
-
- /* Check if the number of regions exceeded the count specified in MPUIR_EL2 */
- cmp \sel, \maxcount
- bge fail_insufficient_regions
-
- /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/
- and \base, \base, #MPU_REGION_MASK
- mov \prbar, #\attr_prbar
- orr \prbar, \prbar, \base
-
- /* Limit address should be inclusive */
- sub \limit, \limit, #1
- and \limit, \limit, #MPU_REGION_MASK
- mov \prlar, #\attr_prlar
- orr \prlar, \prlar, \limit
-
- msr PRSELR_EL2, \sel
- isb
- msr PRBAR_EL2, \prbar
- msr PRLAR_EL2, \prlar
- dsb sy
- isb
-
- add \sel, \sel, #1
-
-1:
-.endm
-
-/*
- * Failure caused due to insufficient MPU regions.
- */
-FUNC_LOCAL(fail_insufficient_regions)
- PRINT("- Selected MPU region is above the implemented number in MPUIR_EL2 -\r\n")
-1: wfe
- b 1b
-END(fail_insufficient_regions)
+#include <asm/mpu/regions.inc>
/*
* Enable EL2 MPU and data cache
diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/include/asm/arm64/sysregs.h
index b593e4028b..7440d495e4 100644
--- a/xen/arch/arm/include/asm/arm64/sysregs.h
+++ b/xen/arch/arm/include/asm/arm64/sysregs.h
@@ -462,6 +462,17 @@
#define ZCR_ELx_LEN_SIZE 9
#define ZCR_ELx_LEN_MASK 0x1ff
+#define REGION_TEXT_PRBAR 0x38 /* SH=11 AP=10 XN=00 */
+#define REGION_RO_PRBAR 0x3A /* SH=11 AP=10 XN=10 */
+#define REGION_DATA_PRBAR 0x32 /* SH=11 AP=00 XN=10 */
+#define REGION_DEVICE_PRBAR 0x22 /* SH=10 AP=00 XN=10 */
+
+#ifdef __ASSEMBLY__
+
+#define WRITE_SYSREG_ASM(v, name) "msr " __stringify(name,) #v
+
+#else /* __ASSEMBLY__ */
+
/* Access to system registers */
#define WRITE_SYSREG64(v, name) do { \
@@ -481,6 +492,8 @@
#define WRITE_SYSREG_LR(v, index) WRITE_SYSREG(v, ICH_LR_REG(index))
#define READ_SYSREG_LR(index) READ_SYSREG(ICH_LR_REG(index))
+#endif /* !__ASSEMBLY__ */
+
#endif /* _ASM_ARM_ARM64_SYSREGS_H */
/*
diff --git a/xen/arch/arm/include/asm/mpu/regions.inc b/xen/arch/arm/include/asm/mpu/regions.inc
new file mode 100644
index 0000000000..47868a1526
--- /dev/null
+++ b/xen/arch/arm/include/asm/mpu/regions.inc
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <asm/mpu.h>
+#include <asm/sysregs.h>
+
+/* Backgroud region enable/disable */
+#define SCTLR_ELx_BR BIT(17, UL)
+
+#define REGION_NORMAL_PRLAR 0x0f /* NS=0 ATTR=111 EN=1 */
+#define REGION_DEVICE_PRLAR 0x09 /* NS=0 ATTR=100 EN=1 */
+
+/*
+ * Macro to prepare and set a EL2 MPU memory region.
+ * We will also create an according MPU memory region entry, which
+ * is a structure of pr_t, in table \prmap.
+ *
+ * sel: region selector
+ * base: reg storing base address
+ * limit: reg storing limit address
+ * prbar: store computed PRBAR_EL2 value
+ * prlar: store computed PRLAR_EL2 value
+ * maxcount: maximum number of EL2 regions supported
+ * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it will be
+ * REGION_DATA_PRBAR
+ * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it will be
+ * REGION_NORMAL_PRLAR
+ *
+ * Preserves maxcount
+ * Output:
+ * sel: Next available region selector index.
+ * Clobbers base, limit, prbar, prlar
+ *
+ * Note that all parameters using registers should be distinct.
+ */
+.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_prbar=REGION_DATA_PRBAR, attr_prlar=REGION_NORMAL_PRLAR
+ /* Check if the region is empty */
+ cmp \base, \limit
+ beq 1f
+
+ /* Check if the number of regions exceeded the count specified in MPUIR_EL2 */
+ cmp \sel, \maxcount
+ bge fail_insufficient_regions
+
+ /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/
+ and \base, \base, #MPU_REGION_MASK
+ mov \prbar, #\attr_prbar
+ orr \prbar, \prbar, \base
+
+ /* Limit address should be inclusive */
+ sub \limit, \limit, #1
+ and \limit, \limit, #MPU_REGION_MASK
+ mov \prlar, #\attr_prlar
+ orr \prlar, \prlar, \limit
+
+ WRITE_SYSREG_ASM(\sel, PRSELR_EL2)
+ isb
+ WRITE_SYSREG_ASM(\prbar, PRBAR_EL2)
+ WRITE_SYSREG_ASM(\prlar, PRLAR_EL2)
+ dsb sy
+ isb
+
+ add \sel, \sel, #1
+
+1:
+.endm
+
+/* Failure caused due to insufficient MPU regions. */
+FUNC_LOCAL(fail_insufficient_regions)
+ PRINT("- Selected MPU region is above the implemented number in MPUIR_EL2 -\r\n")
+1: wfe
+ b 1b
+END(fail_insufficient_regions)
+
+/*
+ * Local variables:
+ * mode: ASM
+ * indent-tabs-mode: nil
+ * End:
+ */
--
2.25.1On 14/04/2025 18:45, Ayan Kumar Halder wrote: > regions.inc is added to hold the common earlyboot MPU regions configurations > between arm64 and arm32. > > prepare_xen_region, fail_insufficient_regions() will be used by both arm32 and > arm64. Thus, they have been moved to regions.inc. Despite my numerous remarks about the commit message style, you did not change it in this patch even though you were respinning the series. For the future, please fix remarks in all the patches. The series is now reviewed. I'll wait a day before committing. ~Michal
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