JAL has a maximium displacement of 2M. To branch further, it needs pairing
with an AUIPC instruction. CALL is a pseudo-op which allows the linker to
pick the appropriate sequence while processing relaxations.
This avoids a build failure of the form:
prelink.o: in function `start':
xen/xen/arch/riscv/riscv64/head.S:28:(.text.header+0x2c):
relocation truncated to fit: R_RISCV_JAL against symbol `calc_phys_offset' defined in .init.text section in prelink.o
make[3]: *** [arch/riscv/Makefile:18: xen-syms] Error 1
when Xen gets large enough, e.g. with CONFIG_UBSAN enabled.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Oleksii Kurochko <oleksii.kurochko@gmail.com>
CC: Anthony PERARD <anthony.perard@vates.tech>
CC: Michal Orzel <michal.orzel@amd.com>
CC: Jan Beulich <jbeulich@suse.com>
CC: Julien Grall <julien@xen.org>
CC: Roger Pau Monné <roger.pau@citrix.com>
CC: Stefano Stabellini <sstabellini@kernel.org>
---
xen/arch/riscv/entry.S | 2 +-
xen/arch/riscv/riscv64/head.S | 12 ++++++------
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/xen/arch/riscv/entry.S b/xen/arch/riscv/entry.S
index bf974655f8b3..4db818ba8d24 100644
--- a/xen/arch/riscv/entry.S
+++ b/xen/arch/riscv/entry.S
@@ -49,7 +49,7 @@ save_to_stack:
REG_S t0, CPU_USER_REGS_SSTATUS(sp)
mv a0, sp
- jal do_trap
+ call do_trap
restore_registers:
/* Restore stack_cpu_regs */
diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S
index 2a1b3dad9191..9c40512e612e 100644
--- a/xen/arch/riscv/riscv64/head.S
+++ b/xen/arch/riscv/riscv64/head.S
@@ -28,7 +28,7 @@ FUNC(start)
add t3, t3, __SIZEOF_POINTER__
bltu t3, t4, .L_clear_bss
- jal reset_stack
+ call reset_stack
/*
* save hart_id ( bootcpu_id ) and dtb_base as a0 and a1 register can
@@ -37,16 +37,16 @@ FUNC(start)
mv s0, a0
mv s1, a1
- jal calc_phys_offset
+ call calc_phys_offset
mv s2, a0
- jal setup_initial_pagetables
+ call setup_initial_pagetables
/* Calculate proper VA after jump from 1:1 mapping */
la a0, .L_primary_switched
sub a0, a0, s2
- jal turn_on_mmu
+ call turn_on_mmu
.L_primary_switched:
/*
@@ -54,11 +54,11 @@ FUNC(start)
* recalculated after jump from 1:1 mapping world as 1:1 mapping
* will be removed soon in start_xen().
*/
- jal reset_stack
+ call reset_stack
/* Xen's boot cpu id is equal to 0 so setup TP register for it */
li a0, 0
- jal setup_tp
+ call setup_tp
/* restore hart_id ( bootcpu_id ) and dtb address */
mv a0, s0
--
2.39.5
On 2/7/25 11:01 PM, Andrew Cooper wrote: > JAL has a maximium displacement of 2M. To branch further, it needs pairing > with an AUIPC instruction. CALL is a pseudo-op which allows the linker to > pick the appropriate sequence while processing relaxations. > > This avoids a build failure of the form: > > prelink.o: in function `start': > xen/xen/arch/riscv/riscv64/head.S:28:(.text.header+0x2c): > relocation truncated to fit: R_RISCV_JAL against symbol `calc_phys_offset' defined in .init.text section in prelink.o > make[3]: *** [arch/riscv/Makefile:18: xen-syms] Error 1 > > when Xen gets large enough, e.g. with CONFIG_UBSAN enabled. > > Signed-off-by: Andrew Cooper<andrew.cooper3@citrix.com> LGTM: Reviewed-by: Oleksii Kurochko<oleksii.kurochko@gmail.com> Thanks. ~ Oleksii > --- > CC: Oleksii Kurochko<oleksii.kurochko@gmail.com> > CC: Anthony PERARD<anthony.perard@vates.tech> > CC: Michal Orzel<michal.orzel@amd.com> > CC: Jan Beulich<jbeulich@suse.com> > CC: Julien Grall<julien@xen.org> > CC: Roger Pau Monné<roger.pau@citrix.com> > CC: Stefano Stabellini<sstabellini@kernel.org> > --- > xen/arch/riscv/entry.S | 2 +- > xen/arch/riscv/riscv64/head.S | 12 ++++++------ > 2 files changed, 7 insertions(+), 7 deletions(-) > > diff --git a/xen/arch/riscv/entry.S b/xen/arch/riscv/entry.S > index bf974655f8b3..4db818ba8d24 100644 > --- a/xen/arch/riscv/entry.S > +++ b/xen/arch/riscv/entry.S > @@ -49,7 +49,7 @@ save_to_stack: > REG_S t0, CPU_USER_REGS_SSTATUS(sp) > > mv a0, sp > - jal do_trap > + call do_trap > > restore_registers: > /* Restore stack_cpu_regs */ > diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S > index 2a1b3dad9191..9c40512e612e 100644 > --- a/xen/arch/riscv/riscv64/head.S > +++ b/xen/arch/riscv/riscv64/head.S > @@ -28,7 +28,7 @@ FUNC(start) > add t3, t3, __SIZEOF_POINTER__ > bltu t3, t4, .L_clear_bss > > - jal reset_stack > + call reset_stack > > /* > * save hart_id ( bootcpu_id ) and dtb_base as a0 and a1 register can > @@ -37,16 +37,16 @@ FUNC(start) > mv s0, a0 > mv s1, a1 > > - jal calc_phys_offset > + call calc_phys_offset > mv s2, a0 > > - jal setup_initial_pagetables > + call setup_initial_pagetables > > /* Calculate proper VA after jump from 1:1 mapping */ > la a0, .L_primary_switched > sub a0, a0, s2 > > - jal turn_on_mmu > + call turn_on_mmu > > .L_primary_switched: > /* > @@ -54,11 +54,11 @@ FUNC(start) > * recalculated after jump from 1:1 mapping world as 1:1 mapping > * will be removed soon in start_xen(). > */ > - jal reset_stack > + call reset_stack > > /* Xen's boot cpu id is equal to 0 so setup TP register for it */ > li a0, 0 > - jal setup_tp > + call setup_tp > > /* restore hart_id ( bootcpu_id ) and dtb address */ > mv a0, s0
© 2016 - 2025 Red Hat, Inc.