[v2] Virtualize architectural LBRs

[RFC PATCH v2 03/10] tools: Add arch LBR feature bits

Posted by Tu Dinh 10 months ago

Signed-off-by: Tu Dinh <ngoc-tu.dinh@vates.tech>
---
 tools/libs/light/libxl_cpuid.c | 3 +++
 tools/misc/xen-cpuid.c         | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/tools/libs/light/libxl_cpuid.c b/tools/libs/light/libxl_cpuid.c
index 063fe86eb7..05be36f258 100644
--- a/tools/libs/light/libxl_cpuid.c
+++ b/tools/libs/light/libxl_cpuid.c
@@ -342,6 +342,9 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *policy, const char* str)
         CPUID_ENTRY(0x00000007,  1, CPUID_REG_EDX),
         MSR_ENTRY(0x10a, CPUID_REG_EAX),
         MSR_ENTRY(0x10a, CPUID_REG_EDX),
+        CPUID_ENTRY(0x0000001C, NA, CPUID_REG_EAX),
+        CPUID_ENTRY(0x0000001C, NA, CPUID_REG_EBX),
+        CPUID_ENTRY(0x0000001C, NA, CPUID_REG_ECX),
 #undef MSR_ENTRY
 #undef CPUID_ENTRY
     };
diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c
index 4c4593528d..4f0fb0a6ea 100644
--- a/tools/misc/xen-cpuid.c
+++ b/tools/misc/xen-cpuid.c
@@ -37,6 +37,9 @@ static const struct {
     { "CPUID 0x00000007:1.edx",     "7d1" },
     { "MSR_ARCH_CAPS.lo",         "m10Al" },
     { "MSR_ARCH_CAPS.hi",         "m10Ah" },
+    { "CPUID 0x0000001c.eax",       "1Ca" },
+    { "CPUID 0x0000001c.ebx",       "1Cb" },
+    { "CPUID 0x0000001c.ecx",       "1Cc" },
 };
 
 #define COL_ALIGN "24"
-- 
2.43.0



Ngoc Tu Dinh | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech

Re: [RFC PATCH v2 03/10] tools: Add arch LBR feature bits

Posted by Jan Beulich 9 months, 3 weeks ago

On 02.01.2025 09:45, Tu Dinh wrote:
> Signed-off-by: Tu Dinh <ngoc-tu.dinh@vates.tech>
> ---
>  tools/libs/light/libxl_cpuid.c | 3 +++
>  tools/misc/xen-cpuid.c         | 3 +++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/tools/libs/light/libxl_cpuid.c b/tools/libs/light/libxl_cpuid.c
> index 063fe86eb7..05be36f258 100644
> --- a/tools/libs/light/libxl_cpuid.c
> +++ b/tools/libs/light/libxl_cpuid.c
> @@ -342,6 +342,9 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *policy, const char* str)
>          CPUID_ENTRY(0x00000007,  1, CPUID_REG_EDX),
>          MSR_ENTRY(0x10a, CPUID_REG_EAX),
>          MSR_ENTRY(0x10a, CPUID_REG_EDX),
> +        CPUID_ENTRY(0x0000001C, NA, CPUID_REG_EAX),
> +        CPUID_ENTRY(0x0000001C, NA, CPUID_REG_EBX),
> +        CPUID_ENTRY(0x0000001C, NA, CPUID_REG_ECX),
>  #undef MSR_ENTRY
>  #undef CPUID_ENTRY
>      };
> diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c
> index 4c4593528d..4f0fb0a6ea 100644
> --- a/tools/misc/xen-cpuid.c
> +++ b/tools/misc/xen-cpuid.c
> @@ -37,6 +37,9 @@ static const struct {
>      { "CPUID 0x00000007:1.edx",     "7d1" },
>      { "MSR_ARCH_CAPS.lo",         "m10Al" },
>      { "MSR_ARCH_CAPS.hi",         "m10Ah" },
> +    { "CPUID 0x0000001c.eax",       "1Ca" },
> +    { "CPUID 0x0000001c.ebx",       "1Cb" },
> +    { "CPUID 0x0000001c.ecx",       "1Cc" },
>  };
>  
>  #define COL_ALIGN "24"

I think this needs folding into patch 2. These tables want to stay in sync at all
times with what the public interface has.

Jan