Signed-off-by: Tu Dinh <ngoc-tu.dinh@vates.tech>
---
 xen/arch/x86/include/asm/msr-index.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index 9cdb5b2625..97df740b04 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -112,6 +112,8 @@
 #define  MCU_OPT_CTRL_GDS_MIT_DIS           (_AC(1, ULL) <<  4)
 #define  MCU_OPT_CTRL_GDS_MIT_LOCK          (_AC(1, ULL) <<  5)
 
+#define MSR_LER_INFO                        0x000001e0
+
 #define MSR_RTIT_OUTPUT_BASE                0x00000560
 #define MSR_RTIT_OUTPUT_MASK                0x00000561
 #define MSR_RTIT_CTL                        0x00000570
@@ -193,6 +195,16 @@
 #define MSR_UARCH_MISC_CTRL                 0x00001b01
 #define  UARCH_CTRL_DOITM                   (_AC(1, ULL) <<  0)
 
+/* Architectural LBR state MSRs */
+#define MSR_LBR_INFO(n)                     (0x00001200 + (n))
+#define MSR_LBR_CTL                         0x000014ce
+#define  LBR_CTL_VALID                      _AC(0x7f000f, ULL)
+#define MSR_LBR_DEPTH                       0x000014cf
+#define MSR_LBR_FROM_IP(n)                  (0x00001500 + (n))
+#define MSR_LBR_TO_IP(n)                    (0x00001600 + (n))
+/* Must be updated along with XSTATE LBR state size */
+#define NUM_MSR_ARCH_LBR_FROM_TO            32
+
 #define MSR_EFER                            _AC(0xc0000080, U) /* Extended Feature Enable Register */
 #define  EFER_SCE                           (_AC(1, ULL) <<  0) /* SYSCALL Enable */
 #define  EFER_LME                           (_AC(1, ULL) <<  8) /* Long Mode Enable */
-- 
2.43.0



Ngoc Tu Dinh | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech

On 02.01.2025 09:45, Tu Dinh wrote:
> --- a/xen/arch/x86/include/asm/msr-index.h
> +++ b/xen/arch/x86/include/asm/msr-index.h
> @@ -112,6 +112,8 @@
>  #define  MCU_OPT_CTRL_GDS_MIT_DIS           (_AC(1, ULL) <<  4)
>  #define  MCU_OPT_CTRL_GDS_MIT_LOCK          (_AC(1, ULL) <<  5)
>  
> +#define MSR_LER_INFO                        0x000001e0
> +
>  #define MSR_RTIT_OUTPUT_BASE                0x00000560
>  #define MSR_RTIT_OUTPUT_MASK                0x00000561
>  #define MSR_RTIT_CTL                        0x00000570
> @@ -193,6 +195,16 @@
>  #define MSR_UARCH_MISC_CTRL                 0x00001b01
>  #define  UARCH_CTRL_DOITM                   (_AC(1, ULL) <<  0)
>  
> +/* Architectural LBR state MSRs */
> +#define MSR_LBR_INFO(n)                     (0x00001200 + (n))
> +#define MSR_LBR_CTL                         0x000014ce
> +#define  LBR_CTL_VALID                      _AC(0x7f000f, ULL)

While I can see that such a value may be useful at some point, I think it wants
introducing when needed and composing of definitions for the individual bits.

Jan