docs/misc/xen-command-line.pandoc | 2 +- xen/arch/x86/Makefile | 2 +- xen/arch/x86/include/asm/processor.h | 6 ++++++ xen/arch/x86/spec_ctrl.c | 4 ++++ 4 files changed, 12 insertions(+), 2 deletions(-)
Transactional Synchronization Extensions are supported on certain Intel's
CPUs only, hence can be put under CONFIG_INTEL build option.
The whole TSX support, even if supported by CPU, may need to be disabled via
options, by microcode or through spec-ctrl, depending on a set of specific
conditions. To make sure nothing gets accidentally runtime-broken all
modifications of global TSX configuration variables is secured by #ifdef's,
while variables themselves redefined to 0, so that ones can't mistakenly be
written to.
Signed-off-by: Sergiy Kibrik <Sergiy_Kibrik@epam.com>
CC: Andrew Cooper <andrew.cooper3@citrix.com>
CC: Jan Beulich <jbeulich@suse.com>
---
changes in v2:
- updated command line doc
- updated patch description
- make tsx_init() stub one line
---
docs/misc/xen-command-line.pandoc | 2 +-
xen/arch/x86/Makefile | 2 +-
xen/arch/x86/include/asm/processor.h | 6 ++++++
xen/arch/x86/spec_ctrl.c | 4 ++++
4 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index 1dea7431fa..2dc946a35d 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -2584,7 +2584,7 @@ pages) must also be specified via the tbuf_size parameter.
### tsx
= <bool>
- Applicability: x86
+ Applicability: x86 with CONFIG_INTEL active
Default: false on parts vulnerable to TAA, true otherwise
Controls for the use of Transactional Synchronization eXtensions.
diff --git a/xen/arch/x86/Makefile b/xen/arch/x86/Makefile
index d902fb7acc..286c003ec3 100644
--- a/xen/arch/x86/Makefile
+++ b/xen/arch/x86/Makefile
@@ -67,7 +67,7 @@ obj-y += srat.o
obj-y += string.o
obj-y += time.o
obj-y += traps.o
-obj-y += tsx.o
+obj-$(CONFIG_INTEL) += tsx.o
obj-y += usercopy.o
obj-y += x86_emulate.o
obj-$(CONFIG_TBOOT) += tboot.o
diff --git a/xen/arch/x86/include/asm/processor.h b/xen/arch/x86/include/asm/processor.h
index c26ef9090c..66463f6a6d 100644
--- a/xen/arch/x86/include/asm/processor.h
+++ b/xen/arch/x86/include/asm/processor.h
@@ -503,9 +503,15 @@ static inline uint8_t get_cpu_family(uint32_t raw, uint8_t *model,
return fam;
}
+#ifdef CONFIG_INTEL
extern int8_t opt_tsx;
extern bool rtm_disabled;
void tsx_init(void);
+#else
+#define opt_tsx 0 /* explicitly indicate TSX is off */
+#define rtm_disabled false /* RTM was not force-disabled */
+static inline void tsx_init(void) {}
+#endif
void update_mcu_opt_ctrl(void);
void set_in_mcu_opt_ctrl(uint32_t mask, uint32_t val);
diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index 40f6ae0170..6b3631e375 100644
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -116,8 +116,10 @@ static int __init cf_check parse_spec_ctrl(const char *s)
if ( opt_pv_l1tf_domu < 0 )
opt_pv_l1tf_domu = 0;
+#ifdef CONFIG_INTEL
if ( opt_tsx == -1 )
opt_tsx = -3;
+#endif
disable_common:
opt_rsb_pv = false;
@@ -2264,6 +2266,7 @@ void __init init_speculation_mitigations(void)
* plausibly value TSX higher than Hyperthreading...), disable TSX to
* mitigate TAA.
*/
+#ifdef CONFIG_INTEL
if ( opt_tsx == -1 && cpu_has_bug_taa && cpu_has_tsx_ctrl &&
((hw_smt_enabled && opt_smt) ||
!boot_cpu_has(X86_FEATURE_SC_VERW_IDLE)) )
@@ -2271,6 +2274,7 @@ void __init init_speculation_mitigations(void)
opt_tsx = 0;
tsx_init();
}
+#endif
/*
* On some SRBDS-affected hardware, it may be safe to relax srb-lock by
--
2.25.1
On 01.07.2024 10:25, Sergiy Kibrik wrote: > Transactional Synchronization Extensions are supported on certain Intel's > CPUs only, hence can be put under CONFIG_INTEL build option. > > The whole TSX support, even if supported by CPU, may need to be disabled via > options, by microcode or through spec-ctrl, depending on a set of specific > conditions. To make sure nothing gets accidentally runtime-broken all > modifications of global TSX configuration variables is secured by #ifdef's, > while variables themselves redefined to 0, so that ones can't mistakenly be > written to. > > Signed-off-by: Sergiy Kibrik <Sergiy_Kibrik@epam.com> Acked-by: Jan Beulich <jbeulich@suse.com> Btw - any reason you didn't Cc Roger? Jan
03.07.24 17:58, Jan Beulich: > On 01.07.2024 10:25, Sergiy Kibrik wrote: >> Transactional Synchronization Extensions are supported on certain Intel's >> CPUs only, hence can be put under CONFIG_INTEL build option. >> >> The whole TSX support, even if supported by CPU, may need to be disabled via >> options, by microcode or through spec-ctrl, depending on a set of specific >> conditions. To make sure nothing gets accidentally runtime-broken all >> modifications of global TSX configuration variables is secured by #ifdef's, >> while variables themselves redefined to 0, so that ones can't mistakenly be >> written to. >> >> Signed-off-by: Sergiy Kibrik <Sergiy_Kibrik@epam.com> > > Acked-by: Jan Beulich <jbeulich@suse.com> > > Btw - any reason you didn't Cc Roger? > oops, forgot to run add_maintainers.pl.. cc Roger -Sergiy
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