Hi Ayan
On 2023/7/5 22:21, Ayan Kumar Halder wrote:
>
> On 26/06/2023 04:34, Penny Zheng wrote:
>> CAUTION: This message has originated from an External Source. Please
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>>
>>
>> VSTCR_EL2, Virtualization Secure Translation Control Register，is
>> the control register for stage 2 of the Secure EL1&0 translation regime.
>>
>> VSTCR_EL2.SA defines secure stage 2 translation output address space.
>> To make sure that all stage 2 translations for the Secure PA space
>> access the Secure PA space, we keep SA bit as 0.
>> VSTCR_EL2.SC is NS check enable bit.
>> To make sure that Stage 2 NS configuration is checked against stage 1
>> NS configuration in EL1&0 translation regime for the given address, and
>> generates a fault if they are different, we set SC bit 1.
>>
>> Signed-off-by: Penny Zheng <penny.zheng@arm.com>
>> Signed-off-by: Wei Chen <wei.chen@arm.com>
>> ---
>> v3:
>> - new commit
>> ---
>> xen/arch/arm/include/asm/arm64/sysregs.h | 6 ++++++
>> xen/arch/arm/mpu/p2m.c | 17 ++++++++++++++++-
>> 2 files changed, 22 insertions(+), 1 deletion(-)
>>
>> diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h
>> b/xen/arch/arm/include/asm/arm64/sysregs.h
>> index ab0e6a97d3..35d7da411d 100644
>> --- a/xen/arch/arm/include/asm/arm64/sysregs.h
>> +++ b/xen/arch/arm/include/asm/arm64/sysregs.h
>> @@ -512,6 +512,12 @@
>> /* MPU Protection Region Enable Register encode */
>> #define PRENR_EL2 S3_4_C6_C1_1
>>
>> +/* Virtualization Secure Translation Control Register */
>> +#define VSTCR_EL2 S3_4_C2_C6_2
>> +#define VSTCR_EL2_RES1_SHIFT 31
>> +#define VSTCR_EL2_SA ~(_AC(0x1,UL)<<30)
>> +#define VSTCR_EL2_SC (_AC(0x1,UL)<<20)
>> +
>> #endif
>>
>> #ifdef CONFIG_ARM_SECURE_STATE
>> diff --git a/xen/arch/arm/mpu/p2m.c b/xen/arch/arm/mpu/p2m.c
>> index 04c44825cb..a7a3912a9a 100644
>> --- a/xen/arch/arm/mpu/p2m.c
>> +++ b/xen/arch/arm/mpu/p2m.c
>> @@ -10,7 +10,7 @@
>>
>> void __init setup_virt_paging(void)
>> {
>> - uint64_t val = 0;
>> + uint64_t val = 0, val2 = 0;
>> bool p2m_vmsa = true;
>>
>> /* PA size */
>> @@ -76,6 +76,21 @@ void __init setup_virt_paging(void)
>>
>> WRITE_SYSREG(val, VTCR_EL2);
> #ifdef CONFIG_ARM_64
>>
>> + /*
>> + * VSTCR_EL2.SA defines secure stage 2 translation output address
>> space.
>> + * To make sure that all stage 2 translations for the Secure PA
>> space
>> + * access the Secure PA space, we keep SA bit as 0.
>> + *
>> + * VSTCR_EL2.SC is NS check enable bit.
>> + * To make sure that Stage 2 NS configuration is checked against
>> stage 1
>> + * NS configuration in EL1&0 translation regime for the given
>> address, and
>> + * generates a fault if they are different, we set SC bit 1.
>> + */
>> + val2 = 1 << VSTCR_EL2_RES1_SHIFT;
>> + val2 &= VSTCR_EL2_SA;
>> + val2 |= VSTCR_EL2_SC;
>> + WRITE_SYSREG(val2, VSTCR_EL2);
> #endif
Understood, will fix.
>> +
>> return;
>>
>> fault:
>> --
>> 2.25.1
>>
>>