Shared caches in multi-core CPU architectures represent a problem for
predictability of memory access latency. This jeopardizes applicability
of many Arm platform in real-time critical and mixed-criticality
scenarios. We introduce support for cache partitioning with page
coloring, a transparent software technique that enables isolation
between domains and Xen, and thus avoids cache interference.

When creating a domain, a simple syntax (e.g. `0-3` or `4-11`) allows
the user to define assignments of cache partitions ids, called colors,
where assigning different colors guarantees no mutual eviction on cache
will ever happen. This instructs the Xen memory allocator to provide
the i-th color assignee only with pages that maps to color i, i.e. that
are indexed in the i-th cache partition.

The proposed implementation supports the dom0less feature.
The proposed implementation doesn't support the static-mem feature.
The solution has been tested in several scenarios, including Xilinx Zynq
MPSoCs.

v4 global changes:
- added "llc" acronym (Last Level Cache) in multiple places in code
  (e.g. coloring.{c|h} -> llc_coloring.{c|h}) to better describe the
  feature and to remove ambiguity with too generic "colors". "llc" is also
  shorter than "cache"
- reordered again patches since code is now splitted in common + arch

Carlo Nonato (8):
  xen/common: add cache coloring common code
  xen/arm: add cache coloring initialization
  xen: extend domctl interface for cache coloring
  tools: add support for cache coloring configuration
  xen/arm: add support for cache coloring configuration via device-tree
  xen/arm: use colored allocator for p2m page tables
  Revert "xen/arm: Remove unused BOOT_RELOC_VIRT_START"
  xen/arm: add cache coloring support for Xen

Luca Miccio (3):
  xen/arm: add Dom0 cache coloring support
  xen: add cache coloring allocator for domains
  xen/arm: add Xen cache colors command line parameter

 docs/man/xl.cfg.5.pod.in                |  10 +
 docs/misc/arm/cache-coloring.rst        | 223 +++++++++++++
 docs/misc/arm/device-tree/booting.txt   |   4 +
 docs/misc/xen-command-line.pandoc       |  61 ++++
 tools/libs/ctrl/xc_domain.c             |  17 +
 tools/libs/light/libxl_create.c         |   2 +
 tools/libs/light/libxl_types.idl        |   1 +
 tools/xl/xl_parse.c                     |  38 ++-
 xen/arch/Kconfig                        |  29 ++
 xen/arch/arm/Kconfig                    |   1 +
 xen/arch/arm/Makefile                   |   1 +
 xen/arch/arm/alternative.c              |   9 +-
 xen/arch/arm/arm64/head.S               |  50 +++
 xen/arch/arm/arm64/mm.c                 |  26 +-
 xen/arch/arm/domain_build.c             |  35 ++-
 xen/arch/arm/include/asm/config.h       |   4 +-
 xen/arch/arm/include/asm/llc_coloring.h |  65 ++++
 xen/arch/arm/include/asm/mm.h           |  10 +-
 xen/arch/arm/include/asm/processor.h    |  16 +
 xen/arch/arm/llc_coloring.c             | 397 ++++++++++++++++++++++++
 xen/arch/arm/mm.c                       |  95 +++++-
 xen/arch/arm/p2m.c                      |  11 +-
 xen/arch/arm/psci.c                     |   9 +-
 xen/arch/arm/setup.c                    |  82 ++++-
 xen/arch/arm/smpboot.c                  |   9 +-
 xen/arch/arm/xen.lds.S                  |   2 +-
 xen/common/Kconfig                      |   3 +
 xen/common/domain.c                     |  23 +-
 xen/common/domctl.c                     |  12 +-
 xen/common/keyhandler.c                 |   4 +
 xen/common/page_alloc.c                 | 247 +++++++++++++--
 xen/include/public/domctl.h             |   6 +-
 xen/include/xen/llc_coloring.h          |  63 ++++
 xen/include/xen/mm.h                    |  33 ++
 xen/include/xen/sched.h                 |   9 +
 35 files changed, 1552 insertions(+), 55 deletions(-)
 create mode 100644 docs/misc/arm/cache-coloring.rst
 create mode 100644 xen/arch/arm/include/asm/llc_coloring.h
 create mode 100644 xen/arch/arm/llc_coloring.c
 create mode 100644 xen/include/xen/llc_coloring.h

-- 
2.34.1

On 23.01.2023 16:47, Carlo Nonato wrote:
> Shared caches in multi-core CPU architectures represent a problem for
> predictability of memory access latency. This jeopardizes applicability
> of many Arm platform in real-time critical and mixed-criticality
> scenarios. We introduce support for cache partitioning with page
> coloring, a transparent software technique that enables isolation
> between domains and Xen, and thus avoids cache interference.
> 
> When creating a domain, a simple syntax (e.g. `0-3` or `4-11`) allows
> the user to define assignments of cache partitions ids, called colors,
> where assigning different colors guarantees no mutual eviction on cache
> will ever happen. This instructs the Xen memory allocator to provide
> the i-th color assignee only with pages that maps to color i, i.e. that
> are indexed in the i-th cache partition.
> 
> The proposed implementation supports the dom0less feature.
> The proposed implementation doesn't support the static-mem feature.
> The solution has been tested in several scenarios, including Xilinx Zynq
> MPSoCs.
> 
> v4 global changes:
> - added "llc" acronym (Last Level Cache) in multiple places in code
>   (e.g. coloring.{c|h} -> llc_coloring.{c|h}) to better describe the

Please can you use dashes in favor of underscores in the names of new
files?

Jan

Hi Jan,

On Mon, Jan 23, 2023 at 4:52 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 23.01.2023 16:47, Carlo Nonato wrote:
> > Shared caches in multi-core CPU architectures represent a problem for
> > predictability of memory access latency. This jeopardizes applicability
> > of many Arm platform in real-time critical and mixed-criticality
> > scenarios. We introduce support for cache partitioning with page
> > coloring, a transparent software technique that enables isolation
> > between domains and Xen, and thus avoids cache interference.
> >
> > When creating a domain, a simple syntax (e.g. `0-3` or `4-11`) allows
> > the user to define assignments of cache partitions ids, called colors,
> > where assigning different colors guarantees no mutual eviction on cache
> > will ever happen. This instructs the Xen memory allocator to provide
> > the i-th color assignee only with pages that maps to color i, i.e. that
> > are indexed in the i-th cache partition.
> >
> > The proposed implementation supports the dom0less feature.
> > The proposed implementation doesn't support the static-mem feature.
> > The solution has been tested in several scenarios, including Xilinx Zynq
> > MPSoCs.
> >
> > v4 global changes:
> > - added "llc" acronym (Last Level Cache) in multiple places in code
> >   (e.g. coloring.{c|h} -> llc_coloring.{c|h}) to better describe the
>
> Please can you use dashes in favor of underscores in the names of new
> files?

Yes, ok.

> Jan

I also forgot to mention that this patch series applies on top of the
most recent
version of Julien's series (https://marc.info/?l=xen-devel&m=167360469228247).

Thanks.