This is the minimum bodge required to stop guests crashing on Sapphire Rapids
hardware.
Note that both Arch LBR and safely (in terms of migration) enumerating
PDCM/MSR_PERF_CAPS depend on improved MSR levelling support which is still not
yet complete.
i.e. We cannot do the second half (enumerating LBR_FORMAT=0x3f) yet because
we'll make it more likely for VMs to crash in migrate.
Andrew Cooper (2):
x86/vmx: Calculate model-specific LBRs once at start of day
x86/vmx: Support for CPUs without model-specific LBR
xen/arch/x86/hvm/vmx/vmx.c | 307 +++++++++++++++++++++++----------------------
1 file changed, 155 insertions(+), 152 deletions(-)
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2.11.0