[v4] Arm: Enable GICv3 for AArch32

[XEN v4 11/11] xen/Arm: GICv3: Enable GICv3 for AArch32

Posted by Ayan Kumar Halder 3 years, 2 months ago

One can now use GICv3 on AArch32 systems. However, ITS is not supported.
The reason being currently we are trying to validate GICv3 on an AArch32_v8R
system. Refer ARM DDI 0568A.c ID110520, B1.3.1,
"A Generic Interrupt Controller (GIC) implemented with an Armv8-R PE must not
implement LPI support."

By default GICv3 is disabled on AArch32 and enabled on AArch64.

Updated SUPPORT.md to state that GICv3 on Arm32 is not security supported.

Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
---

Changed from :-
v1 - 1. Remove "ARM_64 || ARM_32" as it is always true.
2. Updated SUPPORT.md.

v2 - 1. GICv3 is enabled by default only on ARM_64.
2. Updated SUPPORT.md.

v3 - 1. GICv3 is not selected by ARM_64. Rather, it is optionally
enabled. 
2. GICv3 is disabled by default on ARM_32.

 SUPPORT.md                            | 7 +++++++
 xen/arch/arm/Kconfig                  | 9 +++++----
 xen/arch/arm/include/asm/cpufeature.h | 1 +
 3 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/SUPPORT.md b/SUPPORT.md
index ab71464cf6..295369998e 100644
--- a/SUPPORT.md
+++ b/SUPPORT.md
@@ -76,6 +76,13 @@ For the Cortex A57 r0p0 - r1p1, see Errata 832075.
     Status, ARM SMMUv3: Tech Preview
     Status, Renesas IPMMU-VMSA: Supported, not security supported
 
+### ARM/GICv3
+
+GICv3 is an interrupt controller specification designed by Arm.
+
+    Status, Arm64: Security supported
+    Status, Arm32: Supported, not security supported
+
 ### ARM/GICv3 ITS
 
 Extension to the GICv3 interrupt controller to support MSI.
diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
index 52a05f704d..9d0c45f892 100644
--- a/xen/arch/arm/Kconfig
+++ b/xen/arch/arm/Kconfig
@@ -41,16 +41,17 @@ config ARM_EFI
 
 config GICV3
 	bool "GICv3 driver"
-	depends on ARM_64 && !NEW_VGIC
-	default y
+	depends on !NEW_VGIC
+	default n if ARM_32
+	default y if ARM_64
 	---help---
 
 	  Driver for the ARM Generic Interrupt Controller v3.
-	  If unsure, say Y
+	  If unsure, say N for ARM_32 and Y for ARM_64
 
 config HAS_ITS
         bool "GICv3 ITS MSI controller support (UNSUPPORTED)" if UNSUPPORTED
-        depends on GICV3 && !NEW_VGIC
+        depends on GICV3 && !NEW_VGIC && !ARM_32
 
 config HVM
         def_bool y
diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/asm/cpufeature.h
index c86a2e7f29..c62cf6293f 100644
--- a/xen/arch/arm/include/asm/cpufeature.h
+++ b/xen/arch/arm/include/asm/cpufeature.h
@@ -33,6 +33,7 @@
 #define cpu_has_aarch32   (cpu_has_arm || cpu_has_thumb)
 
 #ifdef CONFIG_ARM_32
+#define cpu_has_gicv3     (boot_cpu_feature32(gic) >= 1)
 #define cpu_has_gentimer  (boot_cpu_feature32(gentimer) == 1)
 /*
  * On Armv7, the value 0 is used to indicate that PMUv2 is not
-- 
2.17.1

Re: [XEN v4 11/11] xen/Arm: GICv3: Enable GICv3 for AArch32

Posted by Julien Grall 3 years, 2 months ago

Hi,

On 28/11/2022 15:56, Ayan Kumar Halder wrote:
> One can now use GICv3 on AArch32 systems. However, ITS is not supported.
> The reason being currently we are trying to validate GICv3 on an AArch32_v8R
> system. Refer ARM DDI 0568A.c ID110520, B1.3.1,
> "A Generic Interrupt Controller (GIC) implemented with an Armv8-R PE must not
> implement LPI support."
> 
> By default GICv3 is disabled on AArch32 and enabled on AArch64.
> 
> Updated SUPPORT.md to state that GICv3 on Arm32 is not security supported.
> 
> Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
> ---
> 
> Changed from :-
> v1 - 1. Remove "ARM_64 || ARM_32" as it is always true.
> 2. Updated SUPPORT.md.
> 
> v2 - 1. GICv3 is enabled by default only on ARM_64.
> 2. Updated SUPPORT.md.
> 
> v3 - 1. GICv3 is not selected by ARM_64. Rather, it is optionally
> enabled.
> 2. GICv3 is disabled by default on ARM_32.
> 
>   SUPPORT.md                            | 7 +++++++
>   xen/arch/arm/Kconfig                  | 9 +++++----
>   xen/arch/arm/include/asm/cpufeature.h | 1 +
>   3 files changed, 13 insertions(+), 4 deletions(-)
> 
> diff --git a/SUPPORT.md b/SUPPORT.md
> index ab71464cf6..295369998e 100644
> --- a/SUPPORT.md
> +++ b/SUPPORT.md
> @@ -76,6 +76,13 @@ For the Cortex A57 r0p0 - r1p1, see Errata 832075.
>       Status, ARM SMMUv3: Tech Preview
>       Status, Renesas IPMMU-VMSA: Supported, not security supported
>   
> +### ARM/GICv3
> +
> +GICv3 is an interrupt controller specification designed by Arm.
> +
> +    Status, Arm64: Security supported
> +    Status, Arm32: Supported, not security supported
> +
>   ### ARM/GICv3 ITS
>   
>   Extension to the GICv3 interrupt controller to support MSI.
> diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
> index 52a05f704d..9d0c45f892 100644
> --- a/xen/arch/arm/Kconfig
> +++ b/xen/arch/arm/Kconfig
> @@ -41,16 +41,17 @@ config ARM_EFI
>   
>   config GICV3
>   	bool "GICv3 driver"
> -	depends on ARM_64 && !NEW_VGIC
> -	default y
> +	depends on !NEW_VGIC
> +	default n if ARM_32
> +	default y if ARM_64
>   	---help---
>   
>   	  Driver for the ARM Generic Interrupt Controller v3.
> -	  If unsure, say Y
> +	  If unsure, say N for ARM_32 and Y for ARM_64

s/ARM_32/32-bit Arm/
s/ARM_64/64-bit Arm/

Or you could use the following wording (used on x86 in similar 
circumstances):

"If unsure, use the default setting."

Cheers,

-- 
Julien Grall

Re: [XEN v4 11/11] xen/Arm: GICv3: Enable GICv3 for AArch32

Posted by Michal Orzel 3 years, 2 months ago

Hi Ayan,

On 28/11/2022 16:56, Ayan Kumar Halder wrote:
> One can now use GICv3 on AArch32 systems. However, ITS is not supported.
> The reason being currently we are trying to validate GICv3 on an AArch32_v8R
> system. Refer ARM DDI 0568A.c ID110520, B1.3.1,
> "A Generic Interrupt Controller (GIC) implemented with an Armv8-R PE must not
> implement LPI support."
> 
> By default GICv3 is disabled on AArch32 and enabled on AArch64.
> 
> Updated SUPPORT.md to state that GICv3 on Arm32 is not security supported.
> 
> Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>

~Michal