[XEN v2 00/12] Arm: Enable GICv3 for AArch32 (v8R)

Ayan Kumar Halder posted 12 patches 1 year, 6 months ago
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git fetch https://gitlab.com/xen-project/patchew/xen tags/patchew/20221031151326.22634-1-ayankuma@amd.com
SUPPORT.md                                 |   6 +
xen/arch/arm/Kconfig                       |   4 +-
xen/arch/arm/gic-v3-lpi.c                  |   8 +-
xen/arch/arm/gic-v3.c                      | 132 ++++++++++-----------
xen/arch/arm/include/asm/arm32/io.h        |  21 ++++
xen/arch/arm/include/asm/arm32/processor.h |   5 +
xen/arch/arm/include/asm/arm32/sysregs.h   |  18 ++-
xen/arch/arm/include/asm/arm64/processor.h |   8 ++
xen/arch/arm/include/asm/arm64/sysregs.h   |   3 +
xen/arch/arm/include/asm/cpregs.h          |  69 +++++++++++
xen/arch/arm/include/asm/cpufeature.h      |   1 +
xen/arch/arm/include/asm/gic_v3_defs.h     |  24 ++--
xen/arch/arm/include/asm/gic_v3_its.h      |   2 +-
xen/arch/arm/include/asm/processor.h       |   6 -
xen/arch/arm/include/asm/vreg.h            |  88 ++++----------
xen/arch/arm/vgic-v3-its.c                 |  17 +--
xen/arch/arm/vgic-v3.c                     |  16 ++-
17 files changed, 255 insertions(+), 173 deletions(-)
[XEN v2 00/12] Arm: Enable GICv3 for AArch32 (v8R)
Posted by Ayan Kumar Halder 1 year, 6 months ago
Hi All,

Please find the following patches to enable GICv3 for AArch32.
This is a pre-requisite to support Xen on Cortex-R52 (AArch32-v8R system)

Let me know your thoughts.

Changes from v1 :-
1. Updated in the changelog for each of the patches.

Ayan Kumar Halder (12):
  xen/Arm: vGICv3: Sysreg emulation is applicable for Aarch64 only
  xen/Arm: GICv3: Move the macros to compute the affnity level to
    arm64/arm32
  xen/Arm: vreg: Support vreg_reg64_* helpers on Aarch32
  xen/Arm: vGICv3: Adapt emulation of GICR_TYPER for AArch32
  xen/Arm: GICv3: Fix GICR_{PENDBASER, PROPBASER} emulation on 32-bit
    host
  xen/Arm: vGICv3: Fix emulation of ICC_SGI1R on AArch32
  xen/Arm: GICv3: Define ICH_LR<n>_EL2 on AArch32
  xen/Arm: GICv3: Define ICH_AP0R<n> and ICH_AP1R<n> for AArch32
  xen/Arm: GICv3: Define GIC registers for AArch32
  xen/Arm: GICv3: Use ULL instead of UL for 64bits
  xen/Arm: GICv3: Define macros to read/write 64 bit
  xen/Arm: GICv3: Enable GICv3 for AArch32

 SUPPORT.md                                 |   6 +
 xen/arch/arm/Kconfig                       |   4 +-
 xen/arch/arm/gic-v3-lpi.c                  |   8 +-
 xen/arch/arm/gic-v3.c                      | 132 ++++++++++-----------
 xen/arch/arm/include/asm/arm32/io.h        |  21 ++++
 xen/arch/arm/include/asm/arm32/processor.h |   5 +
 xen/arch/arm/include/asm/arm32/sysregs.h   |  18 ++-
 xen/arch/arm/include/asm/arm64/processor.h |   8 ++
 xen/arch/arm/include/asm/arm64/sysregs.h   |   3 +
 xen/arch/arm/include/asm/cpregs.h          |  69 +++++++++++
 xen/arch/arm/include/asm/cpufeature.h      |   1 +
 xen/arch/arm/include/asm/gic_v3_defs.h     |  24 ++--
 xen/arch/arm/include/asm/gic_v3_its.h      |   2 +-
 xen/arch/arm/include/asm/processor.h       |   6 -
 xen/arch/arm/include/asm/vreg.h            |  88 ++++----------
 xen/arch/arm/vgic-v3-its.c                 |  17 +--
 xen/arch/arm/vgic-v3.c                     |  16 ++-
 17 files changed, 255 insertions(+), 173 deletions(-)

-- 
2.17.1