https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/best-practices/data-operand-independent-timing-isa-guidance.html
https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/running-average-power-limit-energy-reporting.html
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Jan Beulich <JBeulich@suse.com>
CC: Roger Pau Monné <roger.pau@citrix.com>
CC: Wei Liu <wl@xen.org>
The SDM also lists
#define ARCH_CAPS_OVERCLOCKING_STATUS (_AC(1, ULL) << 23)
but I've got no idea what this is, nor the index of MSR_OVERCLOCKING_STATUS
which is the thing allegedly enumerated by this.
---
xen/arch/x86/include/asm/msr-index.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index 6c250bfcadad..781584953654 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -51,6 +51,9 @@
#define PPIN_ENABLE (_AC(1, ULL) << 1)
#define MSR_PPIN 0x0000004f
+#define MSR_MISC_PACKAGE_CTRL 0x000000bc
+#define PGK_CTRL_ENERGY_FILTER_EN (_AC(1, ULL) << 0)
+
#define MSR_CORE_CAPABILITIES 0x000000cf
#define CORE_CAPS_SPLITLOCK_DETECT (_AC(1, ULL) << 5)
@@ -71,6 +74,9 @@
#define ARCH_CAPS_IF_PSCHANGE_MC_NO (_AC(1, ULL) << 6)
#define ARCH_CAPS_TSX_CTRL (_AC(1, ULL) << 7)
#define ARCH_CAPS_TAA_NO (_AC(1, ULL) << 8)
+#define ARCH_CAPS_MISC_PACKAGE_CTRL (_AC(1, ULL) << 10)
+#define ARCH_CAPS_ENERGY_FILTERING (_AC(1, ULL) << 11)
+#define ARCH_CAPS_DOITM (_AC(1, ULL) << 12)
#define ARCH_CAPS_RRSBA (_AC(1, ULL) << 19)
#define ARCH_CAPS_BHI_NO (_AC(1, ULL) << 20)
@@ -149,6 +155,9 @@
#define PASID_PASID_MASK 0x000fffff
#define PASID_VALID (_AC(1, ULL) << 31)
+#define MSR_UARCH_MISC_CTRL 0x00001b01
+#define UARCH_CTRL_DOITM (_AC(1, ULL) << 0)
+
#define MSR_EFER 0xc0000080 /* Extended Feature Enable Register */
#define EFER_SCE (_AC(1, ULL) << 0) /* SYSCALL Enable */
#define EFER_LME (_AC(1, ULL) << 8) /* Long Mode Enable */
--
2.11.0
On Fri, Jun 10, 2022 at 05:00:50PM +0100, Andrew Cooper wrote: > https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/best-practices/data-operand-independent-timing-isa-guidance.html > https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/running-average-power-limit-energy-reporting.html > > Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> > --- > CC: Jan Beulich <JBeulich@suse.com> > CC: Roger Pau Monné <roger.pau@citrix.com> > CC: Wei Liu <wl@xen.org> > > The SDM also lists > > #define ARCH_CAPS_OVERCLOCKING_STATUS (_AC(1, ULL) << 23) > > but I've got no idea what this is, nor the index of MSR_OVERCLOCKING_STATUS > which is the thing allegedly enumerated by this. > --- > xen/arch/x86/include/asm/msr-index.h | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h > index 6c250bfcadad..781584953654 100644 > --- a/xen/arch/x86/include/asm/msr-index.h > +++ b/xen/arch/x86/include/asm/msr-index.h > @@ -51,6 +51,9 @@ > #define PPIN_ENABLE (_AC(1, ULL) << 1) > #define MSR_PPIN 0x0000004f > > +#define MSR_MISC_PACKAGE_CTRL 0x000000bc Not sure it's worth it, but Intel names this MISC_PACKAGE_CTLS rather than CTRL, same with the bit below in ARCH_CAPABILITIES. Thanks, Roger.
On 10/06/2022 17:00, Andrew Cooper wrote: > https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/best-practices/data-operand-independent-timing-isa-guidance.html > https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/running-average-power-limit-energy-reporting.html > > Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> > --- > CC: Jan Beulich <JBeulich@suse.com> > CC: Roger Pau Monné <roger.pau@citrix.com> > CC: Wei Liu <wl@xen.org> > > The SDM also lists > > #define ARCH_CAPS_OVERCLOCKING_STATUS (_AC(1, ULL) << 23) > > but I've got no idea what this is, nor the index of MSR_OVERCLOCKING_STATUS > which is the thing allegedly enumerated by this. Found it. There's an OVER{C}CLOCKING typo in the SDM. It's MSR 0x195 and new in AlderLake it seems. ~Andrew
On 10.06.2022 19:13, Andrew Cooper wrote: > On 10/06/2022 17:00, Andrew Cooper wrote: >> https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/best-practices/data-operand-independent-timing-isa-guidance.html >> https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/running-average-power-limit-energy-reporting.html >> >> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> >> --- >> CC: Jan Beulich <JBeulich@suse.com> >> CC: Roger Pau Monné <roger.pau@citrix.com> >> CC: Wei Liu <wl@xen.org> >> >> The SDM also lists >> >> #define ARCH_CAPS_OVERCLOCKING_STATUS (_AC(1, ULL) << 23) >> >> but I've got no idea what this is, nor the index of MSR_OVERCLOCKING_STATUS >> which is the thing allegedly enumerated by this. > > > Found it. There's an OVER{C}CLOCKING typo in the SDM. It's MSR 0x195 > and new in AlderLake it seems. With or without bits for it added Reviewed-by: Jan Beulich <jbeulich@suse.com> I'd like to note though that I can't spot such a spelling mistake in version 077 of the SDM (vol 4). Jan
On 13/06/2022 08:46, Jan Beulich wrote: > On 10.06.2022 19:13, Andrew Cooper wrote: >> On 10/06/2022 17:00, Andrew Cooper wrote: >>> https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/best-practices/data-operand-independent-timing-isa-guidance.html >>> https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/running-average-power-limit-energy-reporting.html >>> >>> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> >>> --- >>> CC: Jan Beulich <JBeulich@suse.com> >>> CC: Roger Pau Monné <roger.pau@citrix.com> >>> CC: Wei Liu <wl@xen.org> >>> >>> The SDM also lists >>> >>> #define ARCH_CAPS_OVERCLOCKING_STATUS (_AC(1, ULL) << 23) >>> >>> but I've got no idea what this is, nor the index of MSR_OVERCLOCKING_STATUS >>> which is the thing allegedly enumerated by this. >> >> Found it. There's an OVER{C}CLOCKING typo in the SDM. It's MSR 0x195 >> and new in AlderLake it seems. > With or without bits for it added > Reviewed-by: Jan Beulich <jbeulich@suse.com> > I'd like to note though that I can't spot such a spelling mistake in version > 077 of the SDM (vol 4). That's because it's surprisingly hard to deliberately make a typo... It was OVER LOCKING i.e. no c's rather than 2. ~Andrew
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