https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/branch-history-injection.html
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Jan Beulich <JBeulich@suse.com>
CC: Roger Pau Monné <roger.pau@citrix.com>
CC: Wei Liu <wl@xen.org>
These are defined now, but support in hardware hasn't been released yet.
---
xen/arch/x86/include/asm/msr-index.h | 7 +++++++
xen/include/public/arch-x86/cpufeatureset.h | 3 +++
2 files changed, 10 insertions(+)
diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index 31964b88af7a..6c250bfcadad 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -36,7 +36,12 @@
#define SPEC_CTRL_IBRS (_AC(1, ULL) << 0)
#define SPEC_CTRL_STIBP (_AC(1, ULL) << 1)
#define SPEC_CTRL_SSBD (_AC(1, ULL) << 2)
+#define SPEC_CTRL_IPRED_DIS_U (_AC(1, ULL) << 3)
+#define SPEC_CTRL_IPRED_DIS_S (_AC(1, ULL) << 4)
+#define SPEC_CTRL_RRSBA_DIS_U (_AC(1, ULL) << 5)
+#define SPEC_CTRL_RRSBA_DIS_S (_AC(1, ULL) << 6)
#define SPEC_CTRL_PSFD (_AC(1, ULL) << 7)
+#define SPEC_CTRL_BHI_DIS_S (_AC(1, ULL) << 10)
#define MSR_PRED_CMD 0x00000049
#define PRED_CMD_IBPB (_AC(1, ULL) << 0)
@@ -66,6 +71,8 @@
#define ARCH_CAPS_IF_PSCHANGE_MC_NO (_AC(1, ULL) << 6)
#define ARCH_CAPS_TSX_CTRL (_AC(1, ULL) << 7)
#define ARCH_CAPS_TAA_NO (_AC(1, ULL) << 8)
+#define ARCH_CAPS_RRSBA (_AC(1, ULL) << 19)
+#define ARCH_CAPS_BHI_NO (_AC(1, ULL) << 20)
#define MSR_FLUSH_CMD 0x0000010b
#define FLUSH_CMD_L1D (_AC(1, ULL) << 0)
diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index 0c27f5bbaf37..101698941074 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -304,6 +304,9 @@ XEN_CPUFEATURE(INTEL_PPIN, 12*32+ 0) /* Protected Processor Inventory
/* Intel-defined CPU features, CPUID level 0x00000007:2.edx, word 13 */
XEN_CPUFEATURE(INTEL_PSFD, 13*32+ 0) /*A MSR_SPEC_CTRL.PSFD */
+XEN_CPUFEATURE(IPRED_CTRL, 13*32+ 1) /* MSR_SPEC_CTRL.IPRED_DIS_* */
+XEN_CPUFEATURE(RRSBA_CTRL, 13*32+ 2) /* MSR_SPEC_CTRL.RRSBA_DIS_* */
+XEN_CPUFEATURE(BHI_CTRL, 13*32+ 4) /* MSR_SPEC_CTRL.BHI_DIS_S */
XEN_CPUFEATURE(MCDT_NO, 13*32+ 5) /*A MCDT_NO */
#endif /* XEN_CPUFEATURE */
--
2.11.0