[PATCH RFC 0/6] x86/ioapic: fix edge triggered interrupt migration

Roger Pau Monne posted 6 patches 2 years ago
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xen/arch/x86/include/asm/io_apic.h       |  72 ++++++-------
xen/arch/x86/include/asm/iommu.h         |   3 +-
xen/arch/x86/io_apic.c                   |  81 ++++++++++-----
xen/drivers/passthrough/amd/iommu.h      |   2 +-
xen/drivers/passthrough/amd/iommu_intr.c | 115 +++++++--------------
xen/drivers/passthrough/vtd/extern.h     |   2 +-
xen/drivers/passthrough/vtd/intremap.c   | 125 +++++++++++------------
xen/drivers/passthrough/x86/iommu.c      |   4 +-
xen/include/xen/iommu.h                  |   3 +-
9 files changed, 195 insertions(+), 212 deletions(-)
[PATCH RFC 0/6] x86/ioapic: fix edge triggered interrupt migration
Posted by Roger Pau Monne 2 years ago
Hello,

Following series attempts to solve the issue with IO-APIC edge triggered
interrupts seeing an inconsistent RTE or IRTE when injected while being
migrated.

It's currently RFC because some patches have post commit message notes,
and because I'm not sure if patch 1 is really needed.  I originally had
the idea of suggesting to only backport patch 1 in order to fix the
issue in older releases, while leaving the more complex (and thus
error prone) IOMMU changes in unstable.  Note however that patch 1 is
just a workaround to prevent interrupts seeing inconsistent entries
while being updated, masking the entry just makes the warning go away,
but the interrupt will be lost.

Thanks, Roger.

Roger Pau Monne (6):
  x86/ioapic: set disable hook for masking edge interrupts
  x86/ioapic: add a raw field to RTE struct
  x86/ioapic: RTE modifications must use ioapic_write_entry
  x86/iommu: pass full IO-APIC RTE for remapping table update
  amd/iommu: atomically update remapping entries when possible
  x86/ioapic: mask entry while updating

 xen/arch/x86/include/asm/io_apic.h       |  72 ++++++-------
 xen/arch/x86/include/asm/iommu.h         |   3 +-
 xen/arch/x86/io_apic.c                   |  81 ++++++++++-----
 xen/drivers/passthrough/amd/iommu.h      |   2 +-
 xen/drivers/passthrough/amd/iommu_intr.c | 115 +++++++--------------
 xen/drivers/passthrough/vtd/extern.h     |   2 +-
 xen/drivers/passthrough/vtd/intremap.c   | 125 +++++++++++------------
 xen/drivers/passthrough/x86/iommu.c      |   4 +-
 xen/include/xen/iommu.h                  |   3 +-
 9 files changed, 195 insertions(+), 212 deletions(-)

-- 
2.35.1
Re: [PATCH RFC 0/6] x86/ioapic: fix edge triggered interrupt migration
Posted by Roger Pau Monné 1 year, 11 months ago
On Thu, Apr 21, 2022 at 03:21:08PM +0200, Roger Pau Monne wrote:
> Hello,
> 
> Following series attempts to solve the issue with IO-APIC edge triggered
> interrupts seeing an inconsistent RTE or IRTE when injected while being
> migrated.
> 
> It's currently RFC because some patches have post commit message notes,
> and because I'm not sure if patch 1 is really needed.  I originally had
> the idea of suggesting to only backport patch 1 in order to fix the
> issue in older releases, while leaving the more complex (and thus
> error prone) IOMMU changes in unstable.  Note however that patch 1 is
> just a workaround to prevent interrupts seeing inconsistent entries
> while being updated, masking the entry just makes the warning go away,
> but the interrupt will be lost.

Ping?

Thanks, Roger.
Re: [PATCH RFC 0/6] x86/ioapic: fix edge triggered interrupt migration
Posted by Jan Beulich 1 year, 11 months ago
On 20.05.2022 14:36, Roger Pau Monné wrote:
> On Thu, Apr 21, 2022 at 03:21:08PM +0200, Roger Pau Monne wrote:
>> Hello,
>>
>> Following series attempts to solve the issue with IO-APIC edge triggered
>> interrupts seeing an inconsistent RTE or IRTE when injected while being
>> migrated.
>>
>> It's currently RFC because some patches have post commit message notes,
>> and because I'm not sure if patch 1 is really needed.  I originally had
>> the idea of suggesting to only backport patch 1 in order to fix the
>> issue in older releases, while leaving the more complex (and thus
>> error prone) IOMMU changes in unstable.  Note however that patch 1 is
>> just a workaround to prevent interrupts seeing inconsistent entries
>> while being updated, masking the entry just makes the warning go away,
>> but the interrupt will be lost.
> 
> Ping?

Sorry, the usual thing with RFCs: They take lower priority than other
work items. This series is certainly the first of the several pending
RFC series which I mean to get to, but it's hard to predict when this
would be.

Jan
Re: [PATCH RFC 0/6] x86/ioapic: fix edge triggered interrupt migration
Posted by Roger Pau Monné 1 year, 11 months ago
On Fri, May 20, 2022 at 02:46:39PM +0200, Jan Beulich wrote:
> On 20.05.2022 14:36, Roger Pau Monné wrote:
> > On Thu, Apr 21, 2022 at 03:21:08PM +0200, Roger Pau Monne wrote:
> >> Hello,
> >>
> >> Following series attempts to solve the issue with IO-APIC edge triggered
> >> interrupts seeing an inconsistent RTE or IRTE when injected while being
> >> migrated.
> >>
> >> It's currently RFC because some patches have post commit message notes,
> >> and because I'm not sure if patch 1 is really needed.  I originally had
> >> the idea of suggesting to only backport patch 1 in order to fix the
> >> issue in older releases, while leaving the more complex (and thus
> >> error prone) IOMMU changes in unstable.  Note however that patch 1 is
> >> just a workaround to prevent interrupts seeing inconsistent entries
> >> while being updated, masking the entry just makes the warning go away,
> >> but the interrupt will be lost.
> > 
> > Ping?
> 
> Sorry, the usual thing with RFCs: They take lower priority than other
> work items. This series is certainly the first of the several pending
> RFC series which I mean to get to, but it's hard to predict when this
> would be.

No problem, I don't think it's a super urgent issue: we have always
handled interrupts this way and so far got no noticeable issues (apart
from the log messages reported on the console).

There's a non-trivial amount of IOMMU code changes, so maybe the IOMMU
maintainers could take a stab at those as a start?

Thanks, Roger.