Hello,

The following series aim to solve the issue reported by Joe Jin related
to posted interrupts.

I've decided to send a new version because the previous one was missing
the first patch, and I've also taken the opportunity to address Jan's
comments related to patch 2. It's still missing feedback from Intel
however.

Thanks, Roger.

Roger Pau Monne (2):
  x86/vmx: add ASSERT to prevent syncing PIR to IRR...
  x86/vmx: always sync PIR to IRR before vmentry

 xen/arch/x86/hvm/irq.c     |  7 +++-
 xen/arch/x86/hvm/vmx/vmx.c | 77 ++++++++++++++++----------------------
 2 files changed, 37 insertions(+), 47 deletions(-)

-- 
2.24.0


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On Tue, Nov 26, 2019 at 02:26:46PM +0100, Roger Pau Monne wrote:
> Hello,
> 
> The following series aim to solve the issue reported by Joe Jin related
> to posted interrupts.

Regarding the release blockers email, and the qualification of this
series:

 - a regression introduced since 4.12

This is not a regression, since AFAICT the posted interrupt code has
always been like this.

 - a severe bug of a 4.13 feature

The bug seems to impact people using PCI-passthrough on Intel hardware
that supports posted interrupts (aka APICv). In my opinion, we either
fix it or disable APICv by default (now it's currently enabled by
default).

Thanks, Roger.

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