Receiving this register is useful for introspecting 32-bit Windows when the
event being trapped happened while in ring3.

Signed-off-by: Tamas K Lengyel <tamas@tklengyel.com>
Cc: Razvan Cojocaru <rcojocaru@bitdefender.com>
Cc: Tamas K Lengyel <tamas@tklengyel.com>
Cc: Jan Beulich <jbeulich@suse.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: Wei Liu <wei.liu2@citrix.com>
Cc: Roger Pau Monne <roger.pau@citrix.com>
---
v2: add gdtr limit
v3: use uint32_t to fit the 20 bits
---
 xen/arch/x86/vm_event.c       | 6 ++++++
 xen/include/public/vm_event.h | 5 +++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/vm_event.c b/xen/arch/x86/vm_event.c
index 51c3493b1d..52c2a71fa0 100644
--- a/xen/arch/x86/vm_event.c
+++ b/xen/arch/x86/vm_event.c
@@ -179,6 +179,11 @@ static void vm_event_pack_segment_register(enum x86_segment segment,
         reg->es_sel = seg.sel;
         break;
 
+    case x86_seg_gdtr:
+        reg->gdtr_base = seg.base;
+        reg->gdtr_limit = seg.limit;
+        break;
+
     default:
         ASSERT_UNREACHABLE();
     }
@@ -238,6 +243,7 @@ void vm_event_fill_regs(vm_event_request_t *req)
     vm_event_pack_segment_register(x86_seg_ss, &req->data.regs.x86);
     vm_event_pack_segment_register(x86_seg_ds, &req->data.regs.x86);
     vm_event_pack_segment_register(x86_seg_es, &req->data.regs.x86);
+    vm_event_pack_segment_register(x86_seg_gdtr, &req->data.regs.x86);
 
     req->data.regs.x86.shadow_gs = ctxt.shadow_gs;
     req->data.regs.x86.dr6 = ctxt.dr6;
diff --git a/xen/include/public/vm_event.h b/xen/include/public/vm_event.h
index b2bafc0d77..448c7d5ab9 100644
--- a/xen/include/public/vm_event.h
+++ b/xen/include/public/vm_event.h
@@ -29,7 +29,7 @@
 
 #include "xen.h"
 
-#define VM_EVENT_INTERFACE_VERSION 0x00000004
+#define VM_EVENT_INTERFACE_VERSION 0x00000005
 
 #if defined(__XEN__) || defined(__XEN_TOOLS__)
 
@@ -198,6 +198,7 @@ struct vm_event_regs_x86 {
     uint64_t msr_efer;
     uint64_t msr_star;
     uint64_t msr_lstar;
+    uint64_t gdtr_base;
     uint32_t cs_base;
     uint32_t ss_base;
     uint32_t ds_base;
@@ -211,13 +212,13 @@ struct vm_event_regs_x86 {
     struct vm_event_x86_selector_reg fs;
     struct vm_event_x86_selector_reg gs;
     uint64_t shadow_gs;
+    uint32_t gdtr_limit;
     uint16_t cs_sel;
     uint16_t ss_sel;
     uint16_t ds_sel;
     uint16_t es_sel;
     uint16_t fs_sel;
     uint16_t gs_sel;
-    uint32_t _pad;
 };
 
 /*
-- 
2.20.1


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>>> On 03.05.19 at 00:54, <tamas@tklengyel.com> wrote:
> Receiving this register is useful for introspecting 32-bit Windows when the
> event being trapped happened while in ring3.
> 
> Signed-off-by: Tamas K Lengyel <tamas@tklengyel.com>
> Cc: Razvan Cojocaru <rcojocaru@bitdefender.com>
> Cc: Tamas K Lengyel <tamas@tklengyel.com>
> Cc: Jan Beulich <jbeulich@suse.com>
> Cc: Andrew Cooper <andrew.cooper3@citrix.com>
> Cc: Wei Liu <wei.liu2@citrix.com>
> Cc: Roger Pau Monne <roger.pau@citrix.com>
> ---
> v2: add gdtr limit
> v3: use uint32_t to fit the 20 bits

As per Andrew's response I think v2 is it.

Jan



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On 5/3/19 11:09 AM, Jan Beulich wrote:
>>>> On 03.05.19 at 00:54, <tamas@tklengyel.com> wrote:
>> Receiving this register is useful for introspecting 32-bit Windows when the
>> event being trapped happened while in ring3.
>>
>> Signed-off-by: Tamas K Lengyel <tamas@tklengyel.com>
>> Cc: Razvan Cojocaru <rcojocaru@bitdefender.com>
>> Cc: Tamas K Lengyel <tamas@tklengyel.com>
>> Cc: Jan Beulich <jbeulich@suse.com>
>> Cc: Andrew Cooper <andrew.cooper3@citrix.com>
>> Cc: Wei Liu <wei.liu2@citrix.com>
>> Cc: Roger Pau Monne <roger.pau@citrix.com>
>> ---
>> v2: add gdtr limit
>> v3: use uint32_t to fit the 20 bits
> 
> As per Andrew's response I think v2 is it.

Yes, please. This will also allow us to reuse the existing (remaining) 
pad bits in the future for another limit (for idtr, perhaps).


Thanks,
Razvan

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