xen/arm: gic-v3: disable Group 1 before CPU power-down

[PATCH] xen/arm: gic-v3: disable Group 1 before CPU power-down

Posted by Mykola Kvach 2 days, 13 hours ago

From: Mykola Kvach <mykola_kvach@epam.com>

gicv3_cpu_disable() currently writes 0 to ICC_CTLR_EL1. Unlike
GICC_CTLR in the GICv2 path, ICC_CTLR_EL1 does not enable or disable
physical Group 1 interrupt signalling, so this write only clears
EOImode.

The GICv3 power management rules require the physical group enables in
the CPU interface to be cleared before the redistributor is driven into
ProcessorSleep, otherwise behaviour is UNPREDICTABLE. Xen only enables
Group 1 interrupts on this path, so disable the interface by clearing
ICC_IGRPEN1_EL1 instead.

This appears to be a copy of the GICv2 pattern where the enable control
lives in CTLR, but for GICv3 the enable moved to ICC_IGRPEN1_EL1.

Fixes: bc183a0235e ("xen/arm: Add support for GIC v3")
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
---
 xen/arch/arm/gic-v3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index bc07f97c16..4f0852be2f 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -1028,7 +1028,7 @@ static int gicv3_cpu_init(void)
 
 static void gicv3_cpu_disable(void)
 {
-    WRITE_SYSREG(0, ICC_CTLR_EL1);
+    WRITE_SYSREG(0, ICC_IGRPEN1_EL1);
     isb();
 }
 
-- 
2.43.0

Re: [PATCH] xen/arm: gic-v3: disable Group 1 before CPU power-down

Posted by Orzel, Michal 2 days, 12 hours ago


On 10/04/2026 09:47, Mykola Kvach wrote:
> From: Mykola Kvach <mykola_kvach@epam.com>
> 
> gicv3_cpu_disable() currently writes 0 to ICC_CTLR_EL1. Unlike
> GICC_CTLR in the GICv2 path, ICC_CTLR_EL1 does not enable or disable
> physical Group 1 interrupt signalling, so this write only clears
> EOImode.
> 
> The GICv3 power management rules require the physical group enables in
> the CPU interface to be cleared before the redistributor is driven into
> ProcessorSleep, otherwise behaviour is UNPREDICTABLE. Xen only enables
> Group 1 interrupts on this path, so disable the interface by clearing
> ICC_IGRPEN1_EL1 instead.
> 
> This appears to be a copy of the GICv2 pattern where the enable control
> lives in CTLR, but for GICv3 the enable moved to ICC_IGRPEN1_EL1.
Yes, GICv2 GICC_CTLR combines enable+EOImode in one register.

> 
> Fixes: bc183a0235e ("xen/arm: Add support for GIC v3")
> Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>

~Michal