Some xHCI controller's reset time than 100ms,such as 120ms.
On the on hand, xHCI spec has not specified a timeout value.
Maybe setting xHCI HCRST and CNR bit clear timeout value larger
is a nice thing.As a compromise between compatibility and
latency,we can take 1000ms as a timeout value.
Signed-off-by: WeitaoWangoc <WeitaoWang-oc@zhaoxin.com>
---
src/hw/usb-xhci.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/hw/usb-xhci.c b/src/hw/usb-xhci.c
index 08d1e32..21d091f 100644
--- a/src/hw/usb-xhci.c
+++ b/src/hw/usb-xhci.c
@@ -467,9 +467,9 @@ configure_xhci(void *data)
dprintf(3, "%s: resetting\n", __func__);
writel(&xhci->op->usbcmd, XHCI_CMD_HCRST);
- if (wait_bit(&xhci->op->usbcmd, XHCI_CMD_HCRST, 0, 100) != 0)
+ if (wait_bit(&xhci->op->usbcmd, XHCI_CMD_HCRST, 0, 1000) != 0)
goto fail;
- if (wait_bit(&xhci->op->usbsts, XHCI_STS_CNR, 0, 100) != 0)
+ if (wait_bit(&xhci->op->usbsts, XHCI_STS_CNR, 0, 1000) != 0)
goto fail;
writel(&xhci->op->config, xhci->slots);
--
2.7.4
_______________________________________________
SeaBIOS mailing list -- seabios@seabios.org
To unsubscribe send an email to seabios-leave@seabios.org
On Sun, Aug 09, 2020 at 02:22:23PM -0000, weitaowang-oc@zhaoxin.com wrote: > Some xHCI controller's reset time than 100ms,such as 120ms. > On the on hand, xHCI spec has not specified a timeout value. > Maybe setting xHCI HCRST and CNR bit clear timeout value larger > is a nice thing.As a compromise between compatibility and > latency,we can take 1000ms as a timeout value. Patch looks good to me. Which hardware is this? thanks, Gerd _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-leave@seabios.org
On Wed, Aul 21, 2020 at 06:26:17AM -0000, Gerd Hoffmann wrote: >On Sun, Aug 09, 2020 at 02:22:23PM -0000, weitaowang-oc@zhaoxin.com wrote: >> Some xHCI controller's reset time than 100ms,such as 120ms. >> On the on hand, xHCI spec has not specified a timeout value. >> Maybe setting xHCI HCRST and CNR bit clear timeout value larger >> is a nice thing.As a compromise between compatibility and >> latency,we can take 1000ms as a timeout value. >Patch looks good to me. >Which hardware is this? Thanks very much, It's zhaoxin xHCI controller. Thanks weitao _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-leave@seabios.org
On Thu, Aug 20, 2020 at 01:11:41AM +0000, WeitaoWang-oc wrote: > > On Wed, Aul 21, 2020 at 06:26:17AM -0000, Gerd Hoffmann wrote: > >On Sun, Aug 09, 2020 at 02:22:23PM -0000, weitaowang-oc@zhaoxin.com wrote: > >> Some xHCI controller's reset time than 100ms,such as 120ms. > >> On the on hand, xHCI spec has not specified a timeout value. > >> Maybe setting xHCI HCRST and CNR bit clear timeout value larger > >> is a nice thing.As a compromise between compatibility and > >> latency,we can take 1000ms as a timeout value. > > >Patch looks good to me. > >Which hardware is this? > > Thanks very much, > It's zhaoxin xHCI controller. Patch committed and pushed now. thanks, Gerd _______________________________________________ SeaBIOS mailing list -- seabios@seabios.org To unsubscribe send an email to seabios-leave@seabios.org
© 2016 - 2024 Red Hat, Inc.