[PATCH v2 0/2] Add K230 SoC GPIO controller support

guochun.wang@foxmail.com posted 2 patches 2 weeks, 5 days ago
Only 0 patches received!
There is a newer version of this series
MAINTAINERS                  |   3 +
hw/gpio/Kconfig              |   3 +
hw/gpio/k230_gpio.c          | 362 ++++++++++++++++++++++++++++++
hw/gpio/meson.build          |   1 +
hw/riscv/Kconfig             |   1 +
hw/riscv/k230.c              |  27 ++-
include/hw/gpio/k230_gpio.h  |  73 +++++
include/hw/riscv/k230.h      |   5 +
tests/qtest/k230-gpio-test.c | 521 +++++++++++++++++++++++++++++++++++
tests/qtest/meson.build      |   2 +-
10 files changed, 991 insertions(+), 7 deletions(-)
create mode 100644 hw/gpio/k230_gpio.c
create mode 100644 include/hw/gpio/k230_gpio.h
create mode 100644 tests/qtest/k230-gpio-test.c
[PATCH v2 0/2] Add K230 SoC GPIO controller support
Posted by guochun.wang@foxmail.com 2 weeks, 5 days ago
From: guochun wang <guochun.wang@foxmail.com>

The Kendryte K230 SoC contains two APB GPIO controllers derived from
the Synopsys DesignWare APB GPIO (the Linux gpio-k230 driver is itself
based on gpio-dwapb.c, and shares the same register layout), with a
Canaan-specific compatible ("canaan,k230-apb-gpio") and hardlock
integration. This series implements the device model, wires it into
the K230 SoC, and adds qtest coverage.

Patch 1 implements the controller model following the K230 Technical
Reference Manual v0.3.1: software control mode (DR/DDR/CTL), external
port multiplexing, per-pin IRQ output, edge and level interrupt
detection, EOI/mask/gating logic, DDR/CTL mode switching with pending
interrupt preservation, and three-phase Resettable API support with
VMState migration. It also instantiates the two controllers (gpio0 at
0x9140B000, gpio1 at 0x9140C000) in the K230 SoC, replacing the
previous unimplemented-device placeholders, and wires each controller's
32 per-pin IRQ lines to the PLIC (sources 32..63 and 64..95).

Patch 2 adds 16 qtest cases covering reset values, edge and level
interrupts (rising/falling/both-edge, active-high/active-low), EOI
clearing, INTEN gating and INTMASK masking, mode-switching behaviour,
PLIC claim/complete flow, and the second controller instance.

Hardware control mode, debounce logic, the combined interrupt output,
and clock-domain synchronization are intentionally not modelled; they
have no observable effect under QEMU and are documented in the patch 1
commit message.

The series has been tested against the Linux gpio-k230 driver and the
existing K230 qtest suite.

Changelog for version 2:
  - Resend the patch series because the v1 submission was not properly
    threaded (the cover letter and the two patches were not linked by
    In-Reply-To/References, so they appeared as separate threads on the
    list / in patchwork).
  - No code changes; the patches are functionally identical to v1.

guochun wang (2):
  hw/gpio: add K230 GPIO controller model
  tests/qtest: add K230 GPIO controller test

 MAINTAINERS                  |   3 +
 hw/gpio/Kconfig              |   3 +
 hw/gpio/k230_gpio.c          | 362 ++++++++++++++++++++++++++++++
 hw/gpio/meson.build          |   1 +
 hw/riscv/Kconfig             |   1 +
 hw/riscv/k230.c              |  27 ++-
 include/hw/gpio/k230_gpio.h  |  73 +++++
 include/hw/riscv/k230.h      |   5 +
 tests/qtest/k230-gpio-test.c | 521 +++++++++++++++++++++++++++++++++++
 tests/qtest/meson.build      |   2 +-
 10 files changed, 991 insertions(+), 7 deletions(-)
 create mode 100644 hw/gpio/k230_gpio.c
 create mode 100644 include/hw/gpio/k230_gpio.h
 create mode 100644 tests/qtest/k230-gpio-test.c

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2.43.0