We support up to 6 levels, but those are encoded as 10b according to the
AMD IOMMU spec (chapter 3.3.1, Extended Feature Register).
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
hw/i386/amd_iommu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h
index aeef802364..874030582d 100644
--- a/hw/i386/amd_iommu.h
+++ b/hw/i386/amd_iommu.h
@@ -165,8 +165,8 @@
#define AMDVI_DTE_UPPER_QUAD_RESERVED 0x08f0000000000000
/* AMDVI paging mode */
-#define AMDVI_GATS_MODE (6ULL << 12)
-#define AMDVI_HATS_MODE (6ULL << 10)
+#define AMDVI_GATS_MODE (2ULL << 12)
+#define AMDVI_HATS_MODE (2ULL << 10)
/* IOTLB */
#define AMDVI_IOTLB_MAX_SIZE 1024
--
2.13.6