This patchset implements MIPS Enhanced Virtual Addressing (EVA) support
in QEMU.

The patches are grouped as follows:

 - Patches 1-3: Preliminary fixes.
   A few fixes are made for issues spotted during development.

 - Patch 4: CP0_EBase.WG (write gate).
   This allows more bits of CP0_EBase to be written, which allows the
   exception vector to be moved into a different segment than
   kseg0/kseg1. The related CP0_Config5.CV allows cache error exceptions
   not to be forced to get handled by KSeg1.

 - Patches 5-8: EVA user memory access instructions (CP0_Config5.EVA).
   These allow kernel code to access the user mode view of memory, which
   can no longer be done reliably with normal memory access instructions
   for MUSUK segment access mode (see below).

 - Patches 9-12: Segmentation control (CP0_Config3.SC).
   New cop0 registers are added to reconfigure the virtual memory
   segments. This allows the traditionally fixed virtual memory segments
   to be rearranged, and also allows segments to appear differently
   based on execution mode, for example the access mode MUSUK (Mapped
   User Supervisor, Unmapped Kernel) makes a segment TLB mapped to user
   mode and cached unmapped (direct window to physical) to kernel mode,
   and if EU=1 it is also uncached unmapped to error level (which
   requires the addition of a new MMU mode).

 - Patch 13: P5600 EVA support.
   We add the required capabilities to the P5600 CPU type to allow a
   Malta EVA kernel to be executed.

 - Patch 14: I6400 & MIPS64R2-generic CP0_Ebase.WG support.
   We add WG bit support to these MIPS64 CPUs so the guest kernel can
   run KVM T&E.

Notable limitations:

 - Neither CACHEE (the new EVA instruction) or CACHE (the pre-existing
   non-EVA instruction) generate TLB exceptions for bad addresses, as
   QEMU implements them only with a Cop0 privilege check.

 - No attempt has been made to implement BEV overlays yet, which would
   allow non-standard boot exception vector addresses to be accessed in
   kernel mode, even if the underlying segment is changed. This should
   be done at some point, but wasn't necessary for my purposes.

 - MIPS64 segmentation control (for XKPhys) is functional, however there
   are still a few corner cases that need resolving:
    - EntryHi writability on r6 (you can't write an XKPhys address).
    - R6 style Status.KX,SX,UX writability (KX=0 => SX=0, and SX=0 =>
      UX=0).
    - R6 style addressing special cases & sign extension.
   so I wouldn't recommend enabling it for any CPUs yet. P6600 is the
   only real core that implements it anyway.

Changes in v2:

 - Rebased on 2.9.0
 - New patches 1-3, with some misc fixes
 - CP0_EBase.WG (patch 4):
    - Fix CP0_EBase.WG to be read only when WG is not set in
      CP0_EBase_rw_bitmask, otherwise it will be wrongly probed as
      present.
    - Make cache error exception vector conditional on Config3.SC as
      well as Config5.CV, as per the PRA, and take the CP0C3_SC
      definition from patch 7 (Yongbok).
    - Rename CP0_EBase_rw_bitmask to CP0_EBaseWG_rw_bitmask (Yongbok).
 - Decode EVA load & stores (patch 6)
    - Fix typo in commit message (Yongbok).
    - Use sextract32 (Yongbok).
 - New patch 7, to decode microMIPS EVA loads & stores (Yongbok).
 - Abstract mmu_idx from hflags (patch 9):
    - Also convert reference to hflags & MIPS_HFLAG_KSU in op_helper.c
      to cpu_mmu_index (Yongbok).
 - Add an MMU mode for ERL (patch 10):
    - Add ERL case to log output where cpu_mmu_index() is now used in
      op_helper.c
 - Add segmentation control registers (Patch 11):
    - Use ld_tl and ext32s_tl rather than ld32s_tl to avoid big endian
      host, MIPS64 target issues (Yongbok).
    - Add missing break in DMFC0 CP0_SegCtl2 case.
 - Implement segmentation control (Patch 12):
    - Use hwaddr instead of target_ulong for physical addresses in
      get_seg[ctl]_physical_address() (Yongbok).
    - Fix xkphys privilege control based on access mode (am) (Yongbok).
    - Fix xkphys TLB faults to use XTLB.
 - New patch 14.

Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Petar Jovanovic <petar.jovanovic@imgtec.com>

James Hogan (14):
  target/mips: Fix MIPS64 MFC0 UserLocal on BE host
  target/mips: Fix TLBWI shadow flush for EHINV,XI,RI
  target/mips: Weaken TLB flush on UX,SX,KX,ASID changes
  target/mips: Add CP0_Ebase.WG (write gate) support
  target/mips: Prepare loads/stores for EVA
  target/mips: Decode MIPS32 EVA load & store instructions
  target/mips: Decode microMIPS EVA load & store instructions
  target/mips: Check memory permissions with mem_idx
  target/mips: Abstract mmu_idx from hflags
  target/mips: Add an MMU mode for ERL
  target/mips: Add segmentation control registers
  target/mips: Implement segmentation control
  target/mips: Add EVA support to P5600
  target/mips: Enable CP0_EBase.WG on MIPS64 CPUs

 target/mips/cpu.h            |  58 ++++-
 target/mips/helper.c         | 210 ++++++++++++++-----
 target/mips/helper.h         |   3 +-
 target/mips/machine.c        |   9 +-
 target/mips/op_helper.c      |  58 ++++-
 target/mips/translate.c      | 405 ++++++++++++++++++++++++++++++++----
 target/mips/translate_init.c |  17 +-
 7 files changed, 644 insertions(+), 116 deletions(-)

-- 
git-series 0.8.10

Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH 0/14] target/mips: Add Enhanced Virtual Addressing (EVA) support
Message-id: cover.34f8428dbbcaa0611cef759667d281ae508ac91d.1500378931.git-series.james.hogan@imgtec.com
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
888a8b3 target/mips: Enable CP0_EBase.WG on MIPS64 CPUs
ff13d16 target/mips: Add EVA support to P5600
3edc7b0 target/mips: Implement segmentation control
796fdf5 target/mips: Add segmentation control registers
f72fe25 target/mips: Add an MMU mode for ERL
0bcefc0 target/mips: Abstract mmu_idx from hflags
39dc7d8 target/mips: Check memory permissions with mem_idx
d75cb8a target/mips: Decode microMIPS EVA load & store instructions
d92ac8c target/mips: Decode MIPS32 EVA load & store instructions
4f20958 target/mips: Prepare loads/stores for EVA
b99a507 target/mips: Add CP0_Ebase.WG (write gate) support
97df4ad target/mips: Weaken TLB flush on UX, SX, KX, ASID changes
4c8f539 target/mips: Fix TLBWI shadow flush for EHINV, XI, RI
57afc02 target/mips: Fix MIPS64 MFC0 UserLocal on BE host

=== OUTPUT BEGIN ===
Checking PATCH 1/14: target/mips: Fix MIPS64 MFC0 UserLocal on BE host...
Checking PATCH 2/14: target/mips: Fix TLBWI shadow flush for EHINV, XI, RI...
ERROR: space prohibited after that '&' (ctx:WxW)
#44: FILE: target/mips/op_helper.c:2045:
+    XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
                                             ^

ERROR: space prohibited after that '&' (ctx:WxW)
#45: FILE: target/mips/op_helper.c:2046:
+    RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
                                             ^

ERROR: space prohibited after that '&' (ctx:WxW)
#48: FILE: target/mips/op_helper.c:2049:
+    XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
                                             ^

ERROR: space prohibited after that '&' (ctx:WxW)
#49: FILE: target/mips/op_helper.c:2050:
+    RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
                                             ^

total: 4 errors, 0 warnings, 34 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 3/14: target/mips: Weaken TLB flush on UX, SX, KX, ASID changes...
Checking PATCH 4/14: target/mips: Add CP0_Ebase.WG (write gate) support...
ERROR: space prohibited after that '&' (ctx:WxW)
#114: FILE: target/mips/op_helper.c:1519:
+    if (arg1 & (1 << CP0EBase_WG) & mask) {
                                   ^

ERROR: space prohibited after that '&' (ctx:WxW)
#126: FILE: target/mips/op_helper.c:1530:
+    if (arg1 & (1 << CP0EBase_WG) & mask) {
                                   ^

total: 2 errors, 0 warnings, 126 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 5/14: target/mips: Prepare loads/stores for EVA...
Checking PATCH 6/14: target/mips: Decode MIPS32 EVA load & store instructions...
Checking PATCH 7/14: target/mips: Decode microMIPS EVA load & store instructions...
Checking PATCH 8/14: target/mips: Check memory permissions with mem_idx...
Checking PATCH 9/14: target/mips: Abstract mmu_idx from hflags...
Checking PATCH 10/14: target/mips: Add an MMU mode for ERL...
ERROR: trailing statements should be on next line
#94: FILE: target/mips/op_helper.c:98:
+    case 3: cpu_##insn##_error_ra(env, addr, val, retaddr); break;      \

ERROR: trailing statements should be on next line
#102: FILE: target/mips/op_helper.c:1456:
+        case 3: qemu_log(", ERL\n"); break;

ERROR: trailing statements should be on next line
#110: FILE: target/mips/op_helper.c:2251:
+        case 3: qemu_log(", ERL\n"); break;

total: 3 errors, 0 warnings, 79 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 11/14: target/mips: Add segmentation control registers...
Checking PATCH 12/14: target/mips: Implement segmentation control...
ERROR: braces {} are necessary for all arms of this statement
#246: FILE: target/mips/helper.c:836:
+            if ((R != 0 || UX) && (R != 3 || KX) &&
[...]

ERROR: braces {} are necessary for all arms of this statement
#258: FILE: target/mips/helper.c:854:
+            if ((R != 0 || UX) && (R != 3 || KX) &&
[...]

total: 2 errors, 0 warnings, 234 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 13/14: target/mips: Add EVA support to P5600...
Checking PATCH 14/14: target/mips: Enable CP0_EBase.WG on MIPS64 CPUs...
=== OUTPUT END ===

Test command exited with code: 1


---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org

On Tue, Jul 18, 2017 at 02:21:20PM -0700, no-reply@patchew.org wrote:
> Checking PATCH 2/14: target/mips: Fix TLBWI shadow flush for EHINV, XI, RI...
> ERROR: space prohibited after that '&' (ctx:WxW)
> #44: FILE: target/mips/op_helper.c:2045:
> +    XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
>                                              ^
> 
> ERROR: space prohibited after that '&' (ctx:WxW)
> #45: FILE: target/mips/op_helper.c:2046:
> +    RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
>                                              ^
> 
> ERROR: space prohibited after that '&' (ctx:WxW)
> #48: FILE: target/mips/op_helper.c:2049:
> +    XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
>                                              ^
> 
> ERROR: space prohibited after that '&' (ctx:WxW)
> #49: FILE: target/mips/op_helper.c:2050:
> +    RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
>                                              ^
> 
> total: 4 errors, 0 warnings, 34 lines checked

These are false positives. The code looks fine to me. They are binary
bitwise-and operators, not unary address-of operators.

> Your patch has style problems, please review.  If any of these errors
> are false positives report them to the maintainer, see
> CHECKPATCH in MAINTAINERS.

It looks orphaned.

> Checking PATCH 10/14: target/mips: Add an MMU mode for ERL...
> ERROR: trailing statements should be on next line
> #94: FILE: target/mips/op_helper.c:98:
> +    case 3: cpu_##insn##_error_ra(env, addr, val, retaddr); break;      \
> 
> ERROR: trailing statements should be on next line
> #102: FILE: target/mips/op_helper.c:1456:
> +        case 3: qemu_log(", ERL\n"); break;
> 
> ERROR: trailing statements should be on next line
> #110: FILE: target/mips/op_helper.c:2251:
> +        case 3: qemu_log(", ERL\n"); break;
> 
> total: 3 errors, 0 warnings, 79 lines checked

These are all consistent with the surrounding code.

> Checking PATCH 12/14: target/mips: Implement segmentation control...
> ERROR: braces {} are necessary for all arms of this statement
> #246: FILE: target/mips/helper.c:836:
> +            if ((R != 0 || UX) && (R != 3 || KX) &&
> [...]
> 
> ERROR: braces {} are necessary for all arms of this statement
> #258: FILE: target/mips/helper.c:854:
> +            if ((R != 0 || UX) && (R != 3 || KX) &&
> [...]
> 
> total: 2 errors, 0 warnings, 234 lines checked

And these are both pre-existing style issues that the patch hasn't
changed.

Cheers
James