This series fixes five independently reproducible RISC-V issues in QEMU TCG translation and CSR handling. Each patch is independent and references the corresponding QEMU GitLab Work Item.

The series covers:

 - gating RV64-only Xmips instructions on RV32;
 - gating RV64-only XVentanaCondOps instructions on RV32;
 - allowing legal ZALASR loads with rd=x0;
 - restoring writeback for fsgnjn.h and fsgnjx.h under Zfinx/Zhinx;
 - normalizing the implemented Zcmt jvt.mode on writes.

The five reports are QEMU Work Items #4404 through #4408. The runtime witness matrices were executed on clean patched QEMU builds based on the reproduction snapshots; 29 witness and control combinations passed. Current master c513597761d6fc06690b5b7cf10dfb7ab05815d0 was checked separately for source applicability, and all five patches pass checkpatch.pl with zero errors and zero warnings.

The reports were prepared with the assistance of an automated fuzzing and emulation-differential tool and were manually triaged.

wangyang (5):
  target/riscv: gate RV64-only Xmips instructions on XLEN
  target/riscv: gate RV64-only XVentanaCondOps instructions on XLEN
  target/riscv: allow ZALASR loads with rd=x0
  target/riscv: write back fsgnjn.h and fsgnjx.h results
  target/riscv: normalize Zcmt jvt.mode on writes

Changes since v1:
 - Preserve the complete trailing context line in the patch mail and send the series as raw 8-bit SMTP data.