[PATCH v4 0/5] target/riscv: fix privilege, PMP, CFI, envcfg checks

wangyang posted 5 patches 2 weeks, 1 day ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/cover.1789125266.git.wangyang25@otcaix.iscas.ac.cn
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu@processmission.com>, Christoph Muellner <christoph.muellner@vrull.eu>
target/riscv/internals.h                      |  6 ++++
target/riscv/tcg/cpu_helper.c                 | 24 ++++++++++-----
target/riscv/tcg/csr.c                        | 29 +++++++++++++++++++
target/riscv/tcg/insn_trans/trans_rvi.c.inc   |  9 +++++-
.../riscv/tcg/insn_trans/trans_xthead.c.inc   | 12 ++++++--
target/riscv/tcg/op_helper.c                  | 11 ++++---
target/riscv/xthead.decode                    |  5 +++-
7 files changed, 78 insertions(+), 18 deletions(-)
[PATCH v4 0/5] target/riscv: fix privilege, PMP, CFI, envcfg checks
Posted by wangyang 2 weeks, 1 day ago
This series fixes five independent RISC-V emulation issues in the
XTheadCmo, XTheadBb, HLVX/PMP, Zicfilp, and environment-configuration
paths.

The first two patches correct XThead instruction handling. The third
adds the missing final PMP read check for HLVX. The fourth fixes
Zicfilp exception priority for tracked misaligned JALR targets. The
fifth canonicalizes reserved CBIE encoding while preserving the
defined CBIE=11 encoding.

This series is based on 209b2afaface001c7d4d981e38f186afe7b24a50,
the current upstream master.

Validation performed:

  - QEMU 11.1.1 baseline and patched test-case replays passed.
  - HLVX.HU and HLVX.WU execute-only PMP cases and tracked and
    untracked misaligned JALR controls were checked.
  - Every intermediate patch state built for qemu-system-riscv32,
    qemu-system-riscv64, qemu-riscv32, and qemu-riscv64.
  - RV32 XTheadBb imm6 0, 31, 32, and 63 cases pass with the
    extension enabled and remain illegal when it is disabled.
  - The v4 series passes checkpatch.pl, git diff --check, and
    independent apply checks.

Changes since v3:

  - Patch 2 now decodes the RV32 form with @sh5 and the RV64 form with
    @sh6, as suggested by Chao Liu, and adds a dedicated RV32
    translator.
  - The runtime shift-amount mask and the old Reviewed-by tag were
    removed from patch 2; unchanged reviewed patches retain their
    existing Reviewed-by tags.
  - Resend the complete series as a fresh v4 top-level thread.

wangyang (5):
  target/riscv: enforce XTheadCmo U-mode privilege checks
  target/riscv: decode RV32 XTheadBb th.srri shift amount
  target/riscv: require read permission for HLVX accesses
  target/riscv: prioritize Zicfilp checks for misaligned JALR
  target/riscv: canonicalize reserved CBIE encoding

 target/riscv/internals.h                      |  6 ++++
 target/riscv/tcg/cpu_helper.c                 | 24 ++++++++++-----
 target/riscv/tcg/csr.c                        | 29 +++++++++++++++++++
 target/riscv/tcg/insn_trans/trans_rvi.c.inc   |  9 +++++-
 .../riscv/tcg/insn_trans/trans_xthead.c.inc   | 12 ++++++--
 target/riscv/tcg/op_helper.c                  | 11 ++++---
 target/riscv/xthead.decode                    |  5 +++-
 7 files changed, 78 insertions(+), 18 deletions(-)

-- 
2.55.0.windows.2