This patchset adds 59 HVX floating point instructions from Hexagon
revisions v68 and v73 that were missing in qemu. Tests are also added at
the end.
v4: https://lore.kernel.org/qemu-devel/cover.1775843299.git.matheus.bernardino@oss.qualcomm.com/
v3: https://lore.kernel.org/qemu-devel/cover.1775665981.git.matheus.bernardino@oss.qualcomm.com/
v2: https://lore.kernel.org/qemu-devel/cover.1775122853.git.matheus.bernardino@oss.qualcomm.com/
v1: https://lore.kernel.org/qemu-devel/cover.1774271525.git.matheus.bernardino@oss.qualcomm.com/
Changes in v5:
- patch 11: fixed copy-and-paste error (s/vmax/vmin)
- patch 16: replaced float16 value for BF_* constants for
clearity
Brian Cain (1):
tests/docker: Update hexagon cross toolchain to 22.1.0
Matheus Tavares Bernardino (15):
target/hexagon: fix incorrect/too-permissive HVX encodings
target/hexagon/cpu: add HVX IEEE FP extension
hexagon: group cpu configurations in their own struct
hexagon: print info on "-d in_asm" for disabled IEEE FP instructions
target/hexagon: add v68 HVX IEEE float arithmetic insns
target/hexagon: add v68 HVX IEEE float min/max insns
target/hexagon: add v68 HVX IEEE float misc insns
target/hexagon: add v68 HVX IEEE float conversion insns
target/hexagon: add v68 HVX IEEE float compare insns
target/hexagon: add v73 HVX IEEE bfloat16 insns
tests/hexagon: add tests for v68 HVX IEEE float arithmetics
tests/hexagon: add tests for v68 HVX IEEE float min/max
tests/hexagon: add tests for v68 HVX IEEE float conversions
tests/hexagon: add tests for v68 HVX IEEE float comparisons
tests/hexagon: add tests for HVX bfloat
target/hexagon/cpu.h | 10 +-
target/hexagon/cpu_bits.h | 10 +-
target/hexagon/mmvec/hvx_ieee_fp.h | 69 ++++
target/hexagon/mmvec/macros.h | 8 +
target/hexagon/mmvec/mmvec.h | 3 +
target/hexagon/printinsn.h | 2 +-
target/hexagon/translate.h | 1 +
tests/tcg/hexagon/hex_test.h | 32 ++
tests/tcg/hexagon/hvx_misc.h | 73 ++++
target/hexagon/attribs_def.h.inc | 9 +
disas/hexagon.c | 3 +-
target/hexagon/arch.c | 8 +
target/hexagon/cpu.c | 18 +-
target/hexagon/decode.c | 4 +-
target/hexagon/mmvec/hvx_ieee_fp.c | 137 +++++++
target/hexagon/printinsn.c | 7 +-
target/hexagon/translate.c | 5 +-
tests/tcg/hexagon/fp_hvx.c | 226 +++++++++++
tests/tcg/hexagon/fp_hvx_cmp.c | 275 +++++++++++++
tests/tcg/hexagon/fp_hvx_cvt.c | 219 +++++++++++
tests/tcg/hexagon/fp_hvx_disabled.c | 57 +++
target/hexagon/gen_tcg_funcs.py | 11 +
target/hexagon/hex_common.py | 27 ++
target/hexagon/imported/mmvec/encode_ext.def | 126 ++++--
target/hexagon/imported/mmvec/ext.idef | 369 +++++++++++++++++-
target/hexagon/meson.build | 1 +
.../dockerfiles/debian-hexagon-cross.docker | 10 +-
tests/tcg/hexagon/Makefile.target | 14 +
28 files changed, 1686 insertions(+), 48 deletions(-)
create mode 100644 target/hexagon/mmvec/hvx_ieee_fp.h
create mode 100644 target/hexagon/mmvec/hvx_ieee_fp.c
create mode 100644 tests/tcg/hexagon/fp_hvx.c
create mode 100644 tests/tcg/hexagon/fp_hvx_cmp.c
create mode 100644 tests/tcg/hexagon/fp_hvx_cvt.c
create mode 100644 tests/tcg/hexagon/fp_hvx_disabled.c
Range-diff against v4:
1: 1440dd86da = 1: e94d57178d tests/docker: Update hexagon cross toolchain to 22.1.0
2: b9a5a46b82 = 2: 1fe4b8a0fc target/hexagon: fix incorrect/too-permissive HVX encodings
3: 7889db953a = 3: 10fb5b86db target/hexagon/cpu: add HVX IEEE FP extension
4: ac72a36fd8 = 4: 8f9a2e2ccf hexagon: group cpu configurations in their own struct
5: e24b76d95a = 5: 1bdc772e4a hexagon: print info on "-d in_asm" for disabled IEEE FP instructions
6: 8c9ded658c = 6: 8923b6c6bc target/hexagon: add v68 HVX IEEE float arithmetic insns
7: a89b231b2c = 7: 8e274a7a10 target/hexagon: add v68 HVX IEEE float min/max insns
8: 27a5ca1ce3 = 8: 0bd3279ca0 target/hexagon: add v68 HVX IEEE float misc insns
9: 7fecae322c = 9: beca620d2e target/hexagon: add v68 HVX IEEE float conversion insns
10: ebc920dfcf = 10: 96e27588ad target/hexagon: add v68 HVX IEEE float compare insns
11: d408ee2b2c ! 11: 1a25337356 target/hexagon: add v73 HVX IEEE bfloat16 insns
@@ target/hexagon/imported/mmvec/ext.idef: ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_h
+ "Vector IEEE max: bf", VdV.bf[i] = fp_max_bf(VuV.bf[i], VvV.bf[i]);
+ fBFLOAT())
+ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vmin_bf, "Vd32.bf=vmin(Vu32.bf,Vv32.bf)",
-+ "Vector IEEE max: bf", VdV.bf[i] = fp_min_bf(VuV.bf[i], VvV.bf[i]);
++ "Vector IEEE min: bf", VdV.bf[i] = fp_min_bf(VuV.bf[i], VvV.bf[i]);
+ fBFLOAT())
/******************************************************************************
12: cde613d444 = 12: 791f122bfd tests/hexagon: add tests for v68 HVX IEEE float arithmetics
13: 08abae5ee5 = 13: 7fdbc12ed4 tests/hexagon: add tests for v68 HVX IEEE float min/max
14: c20a21aad6 = 14: ec6af07a28 tests/hexagon: add tests for v68 HVX IEEE float conversions
15: 6b473acaf5 = 15: 53e7370709 tests/hexagon: add tests for v68 HVX IEEE float comparisons
16: 10ebb63b81 ! 16: 392114c4c1 tests/hexagon: add tests for HVX bfloat
@@ tests/tcg/hexagon/fp_hvx_cmp.c: static void test_cmp_hf(void)
+
+ /* Common numbers */
+ PREP_TEST();
-+ TEST_CMP_GT(bf, raw_hf((_Float16)2.2), raw_hf((_Float16)2.1));
-+ TEST_CMP_GT(bf, raw_hf((_Float16)0), raw_hf((_Float16)-2.2));
++ TEST_CMP_GT(bf, BF_two, BF_one);
++ TEST_CMP_GT(bf, BF_one, BF_zero);
+ CHECK(bf, 2);
+
+ /* Infinity vs Infinity/NaN */
--
2.37.2