[v3] tests/qtest: Add Intel IOMMU bare-metal test using iommu-testdev

[PATCH v3 0/2] tests/qtest: Add Intel IOMMU bare-metal test using iommu-testdev

Fengyuan Yu posted 2 patches 1 week, 1 day ago

Diff against v1 v2
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/cover.1774421649.git.15fengyuan@gmail.com

Maintainers: "Michael S. Tsirkin" <mst@redhat.com>, Jason Wang <jasowang@redhat.com>, Yi Liu <yi.l.liu@intel.com>, "Clément Mathieu--Drif" <clement.mathieu--drif@bull.com>, Fabiano Rosas <farosas@suse.de>, Laurent Vivier <lvivier@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>, Tao Tang <tangtao1634@phytium.com.cn>

MAINTAINERS |   2 +
tests/qtest/iommu-intel-test.c   | 216 +++++++++++++
tests/qtest/libqos/meson.build   |   3 +
tests/qtest/libqos/qos-intel-iommu.c | 454 +++++++++++++++++++++++++++
tests/qtest/libqos/qos-intel-iommu.h | 185 +++++++++++
tests/qtest/meson.build  |   2 +
6 files changed, 862 insertions(+)
create mode 100644 tests/qtest/iommu-intel-test.c
create mode 100644 tests/qtest/libqos/qos-intel-iommu.c
create mode 100644 tests/qtest/libqos/qos-intel-iommu.h

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[PATCH v3 0/2] tests/qtest: Add Intel IOMMU bare-metal test using iommu-testdev

Posted by Fengyuan Yu 1 week, 1 day ago

Hi,

This patch series adds a bare-metal qtest for the Intel IOMMU (VT-d) using
the iommu-testdev framework. The test exercises address translation paths
without requiring a full guest OS boot.

Motivation
----------

The Intel IOMMU implementation in QEMU supports various translation 
modes. Currently, comprehensive testing of these translation paths 
requires booting a full guest OS with appropriate drivers, which is 
time-consuming and makes regression testing difficult.

This new test fills that gap by using iommu-testdev to trigger DMA
transactions and validate the IOMMU's translation logic directly.

Test Coverage
-------------

The new test provides:
- Legacy pass-through mode (identity mapping)
- Legacy translated mode with 4-level second-level page table walks
- Scalable pass-through mode (PGTT=100b)
- Scalable second-level translation mode (PGTT=010b)
- Scalable first-level translation mode (PGTT=001b)
- Root/Context Entry, PASID Directory/Table Entry configuration
- Complete 48-bit address space translation
- End-to-end DMA verification with memory validation

Testing
-------

QTEST_QEMU_BINARY=./build/qemu-system-x86_64 \
  ./build/tests/qtest/iommu-intel-test --tap -k

Changes v1 -> v2
----------------
- Rebase onto latest upstream to resolve compilation errors
- Add scalable translation mode tests (SLT, FLT, PassThrough)
- Add spec-aligned register field comments for improved readability

Changes v2 -> v3
----------------
- Fix MAINTAINERS: move qos-intel-iommu* to "QTest IOMMU helpers" 
  section, move iommu-intel-test.c entry to patch 2/2, remove
  duplicate entries from x86 general section
- Remove duplicate Q35_IOMMU_BASE macro, use existing
  Q35_HOST_BRIDGE_IOMMU_ADDR instead
- Drop unused QVTD_TM_SCALABLE_NESTED enum value
- Fix parameter alignment in function declarations
- Clarify qvtd_build_dma_attrs() comment: PASID=0 is reached via
  VT-d's no-PASID fallback, not via DMA attributes

Thanks,
Fengyuan

Fengyuan Yu (2):
  tests/qtest/libqos: Add Intel IOMMU helper library
  tests/qtest: Add Intel IOMMU bare-metal test

 MAINTAINERS |   2 +
 tests/qtest/iommu-intel-test.c   | 216 +++++++++++++
 tests/qtest/libqos/meson.build   |   3 +
 tests/qtest/libqos/qos-intel-iommu.c | 454 +++++++++++++++++++++++++++
 tests/qtest/libqos/qos-intel-iommu.h | 185 +++++++++++
 tests/qtest/meson.build  |   2 +
 6 files changed, 862 insertions(+)
 create mode 100644 tests/qtest/iommu-intel-test.c
 create mode 100644 tests/qtest/libqos/qos-intel-iommu.c
 create mode 100644 tests/qtest/libqos/qos-intel-iommu.h

-- 
2.39.5