This commit generates the mb operation. In Wasm, it uses the atomic.fence
instruction as the fence operator [1]. TCI instruction is also generated in
the same way as the original TCI backend using smp_mb().
[1] https://webassembly.github.io/threads/core/syntax/instructions.html#atomic-memory-instructions
Signed-off-by: Kohei Tokunaga <ktokunaga.mail@gmail.com>
---
tcg/wasm64.c | 3 +++
tcg/wasm64/tcg-target.c.inc | 19 +++++++++++++++++++
2 files changed, 22 insertions(+)
diff --git a/tcg/wasm64.c b/tcg/wasm64.c
index bb2651c4dc..895ae062ee 100644
--- a/tcg/wasm64.c
+++ b/tcg/wasm64.c
@@ -573,6 +573,9 @@ static uintptr_t tcg_qemu_tb_exec_tci(CPUArchState *env, const void *v_tb_ptr)
taddr = regs[r1];
oi = regs[r2];
tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr);
+ case INDEX_op_mb:
+ /* Ensure ordering for all kinds */
+ smp_mb();
break;
default:
g_assert_not_reached();
diff --git a/tcg/wasm64/tcg-target.c.inc b/tcg/wasm64/tcg-target.c.inc
index 0f51310700..d187dca970 100644
--- a/tcg/wasm64/tcg-target.c.inc
+++ b/tcg/wasm64/tcg-target.c.inc
@@ -1116,6 +1116,11 @@ static void tcg_out_op_r(TCGContext *s, TCGOpcode op, TCGReg r0)
tcg_out32(s, insn);
}
+static void tcg_out_op_v(TCGContext *s, TCGOpcode op)
+{
+ tcg_out32(s, (uint8_t)op);
+}
+
static void tcg_out_op_ri(TCGContext *s, TCGOpcode op, TCGReg r0, int32_t i1)
{
tcg_insn_unit_tci insn = 0;
@@ -1941,6 +1946,20 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
g_assert_not_reached();
}
+static void tcg_out_mb(TCGContext *s, unsigned a0)
+{
+ tcg_out_op_v(s, INDEX_op_mb);
+
+ /*
+ * Wasm's threading proposal provides atomic.fence instruction as the fence
+ * operator.
+ * https://webassembly.github.io/threads/core/syntax/instructions.html#atomic-memory-instructions
+ */
+ tcg_wasm_out8(s, 0xfe);
+ tcg_wasm_out8(s, 0x03);
+ tcg_wasm_out8(s, 0x00);
+}
+
static void tcg_out_tb_start(TCGContext *s)
{
init_sub_buf();
--
2.43.0