[v7] Generate strided vector loads/stores with tcg nodes

[PATCH v7 0/2] Generate strided vector loads/stores with tcg nodes

Chao Liu posted 2 patches 2 days, 3 hours ago

Diff against v6
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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/cover.1756975571.git.chao.liu@zevorn.cn

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/insn_trans/trans_rvv.c.inc   | 348 ++++++++++++++++++++--
tests/tcg/riscv64/Makefile.softmmu-target |   7 +-
tests/tcg/riscv64/test-vlsseg8e32.S       | 107 +++++++
3 files changed, 444 insertions(+), 18 deletions(-)
create mode 100644 tests/tcg/riscv64/test-vlsseg8e32.S

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[PATCH v7 0/2] Generate strided vector loads/stores with tcg nodes

Posted by Chao Liu 2 days, 3 hours ago

Hi all,

Thanks Nick for the review. In patch v7:

1. Standardize the subject line of patch 1 and remove the trailing period.

2. Split into sub-functions to improve the patch's code readability and
   facilitate review.

3. Use more faster TCG ops, use tcg_gen_andi_tl() instead of tcg_gen_rem_tl().

4. Add a tested-by signature for patch 2, as Eric has already tested it.


History of changes:

patch v6:
- If a strided vector memory access instruction has non-zero vstart, 
  check it through vlse/vsse helpers function.
- Adjust the tcg test Makefile.
  https://lore.kernel.org/qemu-devel/cover.1756906528.git.chao.liu@zevorn.cn/

Patch v5:
- Removed the redundant call to mark_vs_dirty(s) within the
  gen_ldst_stride_main_loop() function.
  https://lore.kernel.org/qemu-riscv/cover.1755609029.git.chao.liu@zevorn.cn/

Patch v4:
- Use ctz32() replace to for-loop
  https://lore.kernel.org/qemu-devel/cover.1755333616.git.chao.liu@yeah.net/

Patch v3:
- Fix the get_log2() function:
  https://lore.kernel.org/qemu-riscv/cover.1755287531.git.chao.liu@yeah.net/T/#t
- Add test for vlsseg8e32 instruction.
- Rebase on top of the latest master.

Patch v2:
- Split the TCG node emulation of the complex strided load/store operation into
  two separate functions to simplify the implementation:
  https://lore.kernel.org/qemu-riscv/20250312155547.289642-1-paolo.savini@embecosm.com/

Patch v1:
- Paolo submitted the initial version of the patch.
  https://lore.kernel.org/qemu-devel/20250211182056.412867-1-paolo.savini@embecosm.com/


Tanks,
Chao

Chao Liu (2):
  target/riscv: Use tcg nodes for strided vector ld/st generation
  tests/tcg/riscv64: Add test for vlsseg8e32 instruction

 target/riscv/insn_trans/trans_rvv.c.inc   | 348 ++++++++++++++++++++--
 tests/tcg/riscv64/Makefile.softmmu-target |   7 +-
 tests/tcg/riscv64/test-vlsseg8e32.S       | 107 +++++++
 3 files changed, 444 insertions(+), 18 deletions(-)
 create mode 100644 tests/tcg/riscv64/test-vlsseg8e32.S

-- 
2.50.1