Hi all,

Thanks Nick for the review. In patch v6, I merge Nick's changes:

1. If a strided vector memory access instruction has non-zero vstart, 
   check it through vlse/vsse helpers function.

   An implementation is permitted to cause an illegal instruction
   if vstart is not 0 and it is set to a value that can not be
   produced implicitly by the implementation, but memory accesses
   will generally always need to deal with page faults.

2. Adjust the tcg test Makefile, use a separate qemu-option for
   vlsseg8e32 case to avoid affect other cases.

see:
https://lore.kernel.org/qemu-riscv/6bqmz4ejwvp4vaj2vve7scqwsvrnjzm657htie7xcvciy54gw6@nbz6hvbombui/


Patch v5:
- Removed the redundant call to mark_vs_dirty(s) within the
  gen_ldst_stride_main_loop() function.
  https://lore.kernel.org/qemu-riscv/cover.1755609029.git.chao.liu@zevorn.cn/

Patch v4:
- Use ctz32() replace to for-loop
  https://lore.kernel.org/qemu-devel/cover.1755333616.git.chao.liu@yeah.net/

Patch v3:
- Fix the get_log2() function:
  https://lore.kernel.org/qemu-riscv/cover.1755287531.git.chao.liu@yeah.net/T/#t
- Add test for vlsseg8e32 instruction.
- Rebase on top of the latest master.

Patch v2:
- Split the TCG node emulation of the complex strided load/store operation into
  two separate functions to simplify the implementation:
  https://lore.kernel.org/qemu-riscv/20250312155547.289642-1-paolo.savini@embecosm.com/


Thanks,
Chao

Chao Liu (2):
  target/riscv: Generate strided vector loads/stores with tcg nodes.
  tests/tcg/riscv64: Add test for vlsseg8e32 instruction

 target/riscv/insn_trans/trans_rvv.c.inc   | 321 +++++++++++++++++++---
 tests/tcg/riscv64/Makefile.softmmu-target |   7 +-
 tests/tcg/riscv64/test-vlsseg8e32.S       | 107 ++++++++
 3 files changed, 396 insertions(+), 39 deletions(-)
 create mode 100644 tests/tcg/riscv64/test-vlsseg8e32.S

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2.50.1