Hi all,
Thanks Richard for the review.
For patch v4, the main modification is to improve the implementation of the
get_log2() function.
+static inline uint32_t get_log2(uint32_t a)
+{
- uint32_t i = 0;
- if (a == 0) {
- return i;
- }
- for (; a > 1;) {
- a >>= 1;
- i++;
- }
+ assert(is_power_of_2(a));
+ return ctz32(a);
+}
patch v3 changes:
- Fix the get_log2() function:
https://lore.kernel.org/qemu-riscv/cover.1755287531.git.chao.liu@yeah.net/T/#t
- Add test for vlsseg8e32 instruction.
- Rebase on top of the latest master.
patch v2 changes:
- Split the TCG node emulation of the complex strided load/store operation into
two separate functions to simplify the implementation:
https://lore.kernel.org/qemu-riscv/20250312155547.289642-1-paolo.savini@embecosm.com/
Best regards,
Chao
Chao Liu (2):
Generate strided vector loads/stores with tcg nodes.
tests/tcg/riscv64: Add test for vlsseg8e32 instruction
target/riscv/insn_trans/trans_rvv.c.inc | 319 ++++++++++++++++++----
tests/tcg/riscv64/Makefile.softmmu-target | 8 +-
tests/tcg/riscv64/test-vlsseg8e32.S | 107 ++++++++
3 files changed, 382 insertions(+), 52 deletions(-)
create mode 100644 tests/tcg/riscv64/test-vlsseg8e32.S
--
2.50.1