[v3] Generate strided vector loads/stores with tcg nodes.

[PATCH v3 0/2] [RISCV/RVV] Generate strided vector loads/stores with tcg nodes.

Chao Liu posted 2 patches 3 months ago

Diff against v1 v2
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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/cover.1755305184.git.chao.liu@yeah.net

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/insn_trans/trans_rvv.c.inc   | 326 ++++++++++++++++++----
tests/tcg/riscv64/Makefile.softmmu-target |   8 +-
tests/tcg/riscv64/test-vlsseg8e32.S       | 107 +++++++
3 files changed, 389 insertions(+), 52 deletions(-)
create mode 100644 tests/tcg/riscv64/test-vlsseg8e32.S

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[PATCH v3 0/2] [RISCV/RVV] Generate strided vector loads/stores with tcg nodes.

Posted by Chao Liu 3 months ago

Hi Paolo, Eric, Daniel,

patch v3 changes:
- Fix the get_log2 cunftion:
  https://lore.kernel.org/qemu-riscv/cover.1755287531.git.chao.liu@yeah.net/T/#t
- Add test for vlsseg8e32 instruction.
- Rebase on top of the latest master.

patch v2 changes:
- Split the TCG node emulation of the complex strided load/store operation into
  two separate functions to simplify the implementation:
  https://lore.kernel.org/qemu-riscv/20250312155547.289642-1-paolo.savini@embecosm.com/


Best regards,

Chao

Chao Liu (2):
  Generate strided vector loads/stores with tcg nodes.
  tests/tcg/riscv64: Add test for vlsseg8e32 instruction

 target/riscv/insn_trans/trans_rvv.c.inc   | 326 ++++++++++++++++++----
 tests/tcg/riscv64/Makefile.softmmu-target |   8 +-
 tests/tcg/riscv64/test-vlsseg8e32.S       | 107 +++++++
 3 files changed, 389 insertions(+), 52 deletions(-)
 create mode 100644 tests/tcg/riscv64/test-vlsseg8e32.S

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2.50.1